A 0.18-μm CMOS analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2531-2540

  Hemati, Saied ^a,b,c   Banihashemi, Amir H ^a,b   Plett, Calvin ^a,b  

^a IEEE   (Canada)

^b CARLETON UNIVERSITY   (Canada)

^c UNIVERSITY OF OTTAWA   (Canada)

Author keywords

Analog iterative decoder; Belief propagation; Current mode circuits; Low density parity check (LDFC) codes; Min sum decoding; Turbo codes

Indexed keywords

ANALOG ITERATIVE DECODERS; BELIEF PROPAGATION; CURRENT-MODE CIRCUITS; LOW-DENSITY PARITY-CHECK (LDFC) CODES; MIN-SUM DECODING;

CODES (SYMBOLS); DECODING; ERROR CORRECTION; ITERATIVE METHODS; MIRRORS; SIGNAL TO NOISE RATIO; TURBO CODES;

CMOS INTEGRATED CIRCUITS;

EID: 33750811602     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.883329     Document Type: Conference Paper

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