A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 9, 2012, Pages 2246-2257

  Yen, Shao Wei ^a   Hung, Shiang Yu ^a   Chen, Chih Lung ^a   Chang, Hsie Chia ^a   Jou, Shyh Jye ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

IEEE 802.15.3c; low density parity check (LDPC) codes; row based layered scheduling

Indexed keywords

CMOS PROCESSS; CODE RATES; CODE STRUCTURE; ENERGY EFFICIENT; HARDWARE COMPLEXITY; HARDWARE EFFICIENCY; IEEE 802.15.3C; ITERATION NUMBERS; LDPC CODES; LDPC DECODER; LOW-DENSITY PARITY-CHECK (LDPC) CODES; MIN-SUM; MULTI RATE; ROUTING SWITCHES;

CMOS INTEGRATED CIRCUITS; FORWARD ERROR CORRECTION; HARDWARE; SCHEDULING; SHIFT REGISTERS;

ENERGY EFFICIENCY;

EID: 84865492858     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2194176     Document Type: Article

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