A New Low-power Turbo Decoder Using HDA-DHDD Stopping Iteration

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1040-1043

  Lee, Wen Ta ^a   Lin, San Ho ^a   Tsai, Chia Chun ^a   Lee, Trong Yen ^a   Hwang, Yuh Shyan ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DECODER ARCHITECTURE; DECODING DELAY; ITERATION ALGORITHMS; LOW POWER; LOW SNR; MEMORY SIZE; SISO DECODER; SLIDING WINDOW; SOFT-IN SOFT-OUT; TURBO DECODERS; VLSI ARCHITECTURES;

ALGORITHMS; WINDOWS;

DECODING;

EID: 33947711520     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464769     Document Type: Conference Paper

References (10)

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