On modeling and evaluation of logic circuits under timing variations

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Volumn , Issue , 2012, Pages 431-436

  Dehbashi, Mehdi ^a   Fey, Gorschwin ^a,b   Roy, Kaushik ^c   Raghunathan, Anand ^c  

^a UNIVERSITY OF BREMEN   (Germany)

^b GERMAN AEROSPACE CENTER DLR   (Germany)

^c PURDUE UNIVERSITY   (United States)

Author keywords

formal verification; logic circuits; timing variations

Indexed keywords

CIRCUIT FREQUENCY; DISCRETE-TIME MODEL; FORMAL VERIFICATIONS; FUNCTIONAL BEHAVIORS; FUNCTIONAL DOMAINS; TIME CONTROL; TIME-ACCURATE; TIMING VARIATIONS;

ELECTRIC NETWORK ANALYSIS; SYSTEMS ANALYSIS; TIMING CIRCUITS;

LOGIC CIRCUITS;

EID: 84872965739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2012.91     Document Type: Conference Paper

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