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Volumn , Issue , 2011, Pages 1566-1571

A new circuit simplification method for error tolerant applications

Author keywords

ATPG; circuit optimization; DCT; Error tolerance; redundancy removal

Indexed keywords

ATPG; CIRCUIT OPTIMIZATION; DCT; ERROR TOLERANCE; REDUNDANCY REMOVAL;

EID: 79957541498     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (42)

References (17)
  • 2
    • 28444494349 scopus 로고    scopus 로고
    • Hardware testing for error tolerant multimedia compression based on liner transforms
    • I. S. Chong and A. Ortega, "Hardware testing for error tolerant multimedia compression based on liner transforms," In Proc. Defect and Fault Tolerance Conference, 2005, pp. 523- 531.
    • Proc. Defect and Fault Tolerance Conference, 2005 , pp. 523-531
    • Chong, I.S.1    Ortega, A.2
  • 4
    • 3042622321 scopus 로고    scopus 로고
    • Defect and error-tolerance in the presence of massive numbers of defects
    • May
    • M. A. Breuer, S. K. Gupta, and T. M. Mak, "Defect and error-tolerance in the presence of massive numbers of defects," IEEE Design and Test Magazine, 21, pp. 216-227, May 2004.
    • (2004) IEEE Design and Test Magazine , vol.21 , pp. 216-227
    • Breuer, M.A.1    Gupta, S.K.2    Mak, T.M.3
  • 6
    • 33846931865 scopus 로고    scopus 로고
    • Threshold testing: Covering bridging and other realistic faults
    • Zhigang Jiang, Sandeep K. Gupta, "Threshold testing: Covering bridging and other realistic faults, " In Proc. Asian Test Symposium , 2005, pp. 390-397.
    • Proc. Asian Test Symposium, 2005 , pp. 390-397
    • Jiang, Z.1    Gupta, S.K.2
  • 7
    • 58249108410 scopus 로고    scopus 로고
    • A Re-design Technique for datapath modules in error tolerant applications
    • D. Shin and S. K. Gupta, "A Re-design Technique for datapath modules in error tolerant applications," In Proc. Asian Test Symposium, 2008, pp. 431-437.
    • Proc. Asian Test Symposium, 2008 , pp. 431-437
    • Shin, D.1    Gupta, S.K.2
  • 14
    • 84941363915 scopus 로고    scopus 로고
    • Redundancy Removal and Simplification of Combinational Circuits
    • P. R. Merion and H. Ahuja, "Redundancy Removal and Simplification of Combinational Circuits," In Proc. VLSI Test Symposium, 1992, pp. 268- 273.
    • Proc. VLSI Test Symposium, 1992 , pp. 268-273
    • Merion, P.R.1    Ahuja, H.2
  • 15
    • 33751114448 scopus 로고    scopus 로고
    • An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
    • Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer, "An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance," In Proc. VLSI Test Symposium, 2006, pp. 130-135.
    • Proc. VLSI Test Symposium, 2006 , pp. 130-135
    • Hsieh, T.-Y.1    Lee, K.-J.2    Breuer, M.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.