Slack redistribution for graceful degradation under voltage overscaling

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 825-831

  Kahng, Andrew B ^a,b   Kang, Seokhyeong ^a   Kumar, Rakesh ^c   Sartori, John ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; AREA OVERHEAD; BASELINE DESIGN; CRITICAL OPERATING POINT; CRITICAL VOLTAGES; DIGITAL IC; ERROR RATE; GRACEFUL DEGRADATION; MAXIMUM ERROR; MICROPROCESSOR DESIGNS; PLACEMENT AND ROUTING; POWER CONSUMPTION; POWER REDUCTIONS; POWER-AWARE; SLACK REDISTRIBUTION; SYSTEM RELIABILITY; TIMING ERRORS; TIMING SLACK; TOLERANCE MECHANISMS; UNDER VOLTAGE; VOLTAGE-SCALING;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

TIME MEASUREMENT;

EID: 77951223419     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419690     Document Type: Conference Paper

References (29)

1. T. Austin, V. Bertacco, D. Blaauw and T. Mudge, "Oppotunities and Challenges for Better Than Worst-Case Design", Proc. Asia and South Pacific Design Automation Conf., 2005, pp. 2-7.
2. T. D. Burd, S. Member, T. A. Pering, A. J. Stratakos and R. W. Brodersen, "A Dynamic Voltage Scaled Microprocessor System", IEEE Journal of Solid-State Circuits, 35(11), 2000, pp. 1571-1580. (Pubitemid 32070549)
3. L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Korkmaz, K. V. Palem and B. Seshasayee, "Ultra-Efficient (Embedded) SOC Architectures Based on Probabilistic CMOS (PCMOS) Technology", Proc. Design Automation and Test in Europe, 2006, pp. 1110-1115.
4. S. Dhar, D. Maksimović and B. Kranzen, "Closed-Loop Adaptive Voltage Scaling Controller for Standard-Cell ASICs", IEEE/ACM Proc. International Symposium on Low Power Electronics and Design, 2002, pp.103-107.
5. D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner and T. Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation", IEEE/ACM Proc. International Symposium on Microarchitecture, 2003, pp. 7-18.
6. J. P. Fishburn and A. E. Dunlop, "Tilos: A Polynomial Programming Approach to Transistor Sizing", Proc. ACM/IEEE International Conference on Computer-Aided Design, 1985, pp. 326-328.
7. S. Ghosh and K. Roy, "CRISTA: A new paradigm for low-power and robust circuit synthesis under parameter variations using critical path isolation", TCAD, November 2007.
8. B. Greskamp, L. Wan, W. R. Karpuzcu, J. J. Cook, J. Torrellas, D. Chen and C. Zilles, "BlueShift: Designing Processors for Timing Speculation from the Ground Up", IEEE International Symposium on High Performance Computer Architecture, 2009, pp. 213-224.
9. P. Gupta, A. B. Kahng and P. Sharma, "A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology", Proc. of International Symposium on Quality Electronic Design, 2005, pp. 421-426.
10. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control", IEEE/ACM Proc. of Design Automation Conference, 2004, pp. 327-330.
11. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Gate-Length Biasing for Runtime-Leakage Control", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(8), 2006, pp. 1475-1485.
12. V. Gutnik and A. Chandrakasan, "An Efficient Controller for Variable Supply-Voltage Low Power Processing", IEEE Proc. Symposium on VLSI Circuits, 1996, pp. 158-159.
13. R. Hegde and N. R. Shanbhag, "Energy-Efficient Signal Processing via Algorithmic Noise-Tolerance", Proc. International Symposium on Low Power Electronics and Design, 1999, pp. 30-35.
14. K. Jeong, A. B. Kahng and H. Yao, "Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization", Proc. of International Symposium on Quality Electronic Design, 2009, pp. 127-134.
15. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs", to appear in IEEE International Symposimum on High-Performance Computer Architecture, January 2010.
16. T. Kehl, "Hardware Self-Tuning and Circuit Performance Monitoring", IEEE International Conference on Computer Deisgn, 1993, pp. 188-192.
17. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt and B. Werner, "Simics: A Full System Simulation Platform", Computer, 35(2), 2002, pp. 50-58.
18. S. Narayanan, G. Lyle, R. Kumar and D. Jones, "Testing the Critical Operating Point (COP) Hypothesis using FPGA Emulation of Timing Errors in Over-Scaled Soft-Processors", IEEE Workshop on Silicon Errors in Logic, 2009.
19. J. Patel, "CMOS Process Variations: A Critical Operation Point Hypothesis", Online Presentation, 2008.
20. S. Sarangi, B. Greskamp, A. Tiwari and J. Torrellas, "EVAL: Utilizing Processors with Variation-Induced Timing Errors", IEEE/ACM International Symposium on Microarchitecture, 2008, pp. 423-434.
21. S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw, "Duet: An Accurate Leakage Estimation and Optimization Tool for Dual-Vt Circuits", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 10(2), 2002, pp. 79-90.
22. E. Chung and Jared Smolens, OpenSPARC T1: Architectural Transplants. http://transplant.sunsource.net/.
23. Intel Corporation, "Enhanced Intel Speed Step Technology for the Intel Pentium M Processor", Microproceesors White Papers, 2004.
24. International Technology Roadmap for Semiconductors 2008 Update., http://www.itrs.net/.
25. Sun OpenSPARC Project., http://www.sun.com/processors/opensparc/.
26. Synopsys Design Compiler User's Manual. http://www.synopsys.com/.
27. Synopsys PrimeTime User's Manual. http://www.synopsys.com/.
28. Cadence SignalStorm User's Manual. http://www.cadence.com/.
29. Cadence SOCEncounter User's Manual. http://www.cadence.com/.