메뉴 건너뛰기




Volumn , Issue , 2011, Pages 950-955

Design of voltage-scalable meta-functions for approximate computing

Author keywords

Approximate Computing; Low Power Design; Meta functions; Voltage Over scaling

Indexed keywords

APPLICATION DOMAINS; APPLICATION LEVEL; APPROXIMATE COMPUTING; BASELINE COUNTERPARTS; COMPUTATIONAL KERNELS; COMPUTING TECHNIQUES; DATA PATHS; DELAY BUDGETING; DESIGN TECHNIQUE; DYNAMIC SEGMENTATION; ERROR RATE; HARDWARE IMPLEMENTATIONS; K-MEANS; LOW-POWER DESIGN; META-FUNCTIONS; MULTI-CYCLE; NET EFFECT; SYSTEM LEVEL SIMULATION; TRANSISTOR-LEVEL SIMULATION; UNDER VOLTAGE; VOLTAGE OVER-SCALING;

EID: 79957536506     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (149)

References (16)
  • 3
    • 70449732733 scopus 로고    scopus 로고
    • Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator
    • Aug.
    • Debabrata Mohapatra et al,. Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator. In ISLPED, Aug. 2009.
    • (2009) ISLPED
    • Mohapatra, D.1
  • 4
    • 18844395593 scopus 로고    scopus 로고
    • Energy aware algorithm design via probabilistic computing: From algorithms and models to Moore's law and novel (semiconductor) devices
    • Krishna V. Palem. Energy aware algorithm design via probabilistic computing: From algorithms and models to Moore's law and novel (semiconductor) devices. In Proc. CASES, pages 113-116, 2003.
    • (2003) Proc. CASES , pp. 113-116
    • Palem, K.V.1
  • 5
    • 15044339297 scopus 로고    scopus 로고
    • Razor: Circuit-level correction of timing errors for low-power operation
    • D. Ernst et al. Razor: Circuit-level correction of timing errors for low-power operation. IEEE Micro, 24(6):10-20, 2004.
    • (2004) IEEE Micro , vol.24 , Issue.6 , pp. 10-20
    • Ernst, D.1
  • 6
    • 54249104938 scopus 로고
    • Crista: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation
    • Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy. Crista: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation. IEEE Trans. on CAD, 26(11):1947-1956, 2007.
    • (1947) IEEE Trans. on CAD , vol.26 , Issue.11 , pp. 2007
    • Ghosh, S.1    Bhunia, S.2    Roy, K.3
  • 8
    • 34548316191 scopus 로고    scopus 로고
    • Process variation tolerant low power DCT architecture
    • April
    • Nilanjan Banerjee, Georgios Karakonstantis, and Kaushik Roy. Process variation tolerant low power DCT architecture. In DATE, April 2007.
    • (2007) DATE
    • Banerjee, N.1    Karakonstantis, G.2    Roy, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.