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Volumn 47, Issue 1, 2012, Pages 35-46

A 28 nm 0.6 v low power DSP for mobile applications

Author keywords

Low power electronics; microprocessors

Indexed keywords

ADVANCED PROCESS; CELL LIBRARY; HIGH-POWER; HIGH-SPEED; LOCAL V; LOW POWER DSP; LOW VOLTAGES; LOW-VOLTAGE; MOBILE APPLICATIONS; MODES OF OPERATION; OPERATING POINTS; STATISTICAL STATIC TIMING ANALYSIS; SYSTEM-ON-CHIP; ULTRALOW VOLTAGE; WIDE SUPPLY VOLTAGE RANGE;

EID: 84655166926     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2169689     Document Type: Article
Times cited : (28)

References (14)
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    • Calhoun, B.H.1    Chandrakasan, A.2
  • 2
    • 77950124718 scopus 로고    scopus 로고
    • Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP
    • mar
    • B. Cheng, D. Dideban, N. Moezi, C. Miller, G. Roy, X. Wang, S. Roy, and A. Asenov, "Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP," IEEE Design and Test of Computers, vol. 27, no. 2, pp. 26-35, Mar. 2010.
    • (2010) IEEE Design and Test of Computers , vol.27 , Issue.2 , pp. 26-35
    • Cheng, B.1    Dideban, D.2    Moezi, N.3    Miller, C.4    Roy, G.5    Wang, X.6    Roy, S.7    Asenov, A.8
  • 3
    • 34247202065 scopus 로고    scopus 로고
    • Variation-driven device sizing for minimum energy sub-threshold circuits
    • J. Kwong and A. Chandrakasan, "Variation-driven device sizing for minimum energy sub-threshold circuits," in Proc. ISLPED, 2006, pp. 8-13.
    • (2006) Proc. ISLPED , pp. 8-13
    • Kwong, J.1    Chandrakasan, A.2
  • 10
    • 0023437909 scopus 로고
    • Static noise margin analysis of MOS SRAM cells
    • Oct
    • E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
    • (1987) IEEE J. Solid-state Circuits , vol.SC-22 , Issue.5 , pp. 748-754
    • Seevinck, E.1    List, F.2    Lohstroh, J.3
  • 12
    • 58049102639 scopus 로고    scopus 로고
    • A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis
    • M. Yamaoka, K. Osada, and T. Kawahara, "A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis," in Proc. ESSCIRC, 2008, pp. 286-289.
    • (2008) Proc. ESSCIRC , pp. 286-289
    • Yamaoka, M.1    Osada, K.2    Kawahara, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.