-
1
-
-
16244415208
-
Characterizing and modeling minimum energy operation for subthreshold circuits
-
B. H. Calhoun and A. Chandrakasan, "Characterizing and modeling minimum energy operation for subthreshold circuits," in Proc. ISLPED, 2004, pp. 90-95.
-
(2004)
Proc. ISLPED
, pp. 90-95
-
-
Calhoun, B.H.1
Chandrakasan, A.2
-
2
-
-
77950124718
-
Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP
-
mar
-
B. Cheng, D. Dideban, N. Moezi, C. Miller, G. Roy, X. Wang, S. Roy, and A. Asenov, "Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP," IEEE Design and Test of Computers, vol. 27, no. 2, pp. 26-35, Mar. 2010.
-
(2010)
IEEE Design and Test of Computers
, vol.27
, Issue.2
, pp. 26-35
-
-
Cheng, B.1
Dideban, D.2
Moezi, N.3
Miller, C.4
Roy, G.5
Wang, X.6
Roy, S.7
Asenov, A.8
-
3
-
-
34247202065
-
Variation-driven device sizing for minimum energy sub-threshold circuits
-
J. Kwong and A. Chandrakasan, "Variation-driven device sizing for minimum energy sub-threshold circuits," in Proc. ISLPED, 2006, pp. 8-13.
-
(2006)
Proc. ISLPED
, pp. 8-13
-
-
Kwong, J.1
Chandrakasan, A.2
-
4
-
-
77952230369
-
A 32 nm high-κ metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation
-
H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, N. Yong-Gee, U. Bhattacharya, and K. Zhang, "A 32 nm high-κ metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 346-347.
-
(2010)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 346-347
-
-
Nho, H.1
Kolar, P.2
Hamzaoglu, F.3
Wang, Y.4
Karl, E.5
Yong-Gee, N.6
Bhattacharya, U.7
Zhang, K.8
-
5
-
-
77952208436
-
2 cell in 32 nm high-κ metal-gate CMOS
-
2 cell in 32 nm high-κ metal-gate CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 348-349.
-
(2010)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 348-349
-
-
Fujimura, Y.1
Hirabayashi, O.2
Sasaki, T.3
Suzuki, A.4
Kawasumi, A.5
Takeyama, Y.6
Kushida, K.7
Fukano, G.8
Katayama, A.9
Niki, Y.10
Yabe, T.11
-
6
-
-
49549116677
-
A single-power-supply 0.7 V 1 GHz 45 nm SRAM with an asymmetrical unit-;3 ratio memory cell
-
A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, and N. Otsuka, "A single-power-supply 0.7 V 1 GHz 45 nm SRAM with an asymmetrical unit-;3 ratio memory cell," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 382-383.
-
(2008)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 382-383
-
-
Kawasumi, A.1
Yabe, T.2
Takeyama, Y.3
Hirabayashi, O.4
Kushida, K.5
Tohata, A.6
Sasaki, T.7
Katayama, A.8
Fukano, G.9
Fujimura, Y.10
Otsuka, N.11
-
7
-
-
33644640188
-
Stable SRAM cell design for the 32 nm node and beyond
-
L. Chang, D. M. Fried, J. Hergenrother, W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, N. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond," in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 128-129.
-
(2005)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 128-129
-
-
Chang, L.1
Fried, D.M.2
Hergenrother, J.3
Sleight, W.4
Dennard, R.H.5
Montoye, R.K.6
Sekaric, L.7
McNab, S.J.8
Topol, N.W.9
Adams, C.D.10
Guarini, K.W.11
Haensch, W.12
-
9
-
-
37749013850
-
A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS
-
L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. Gebara, K. Agarwal, D. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, 2007, pp. 252-253.
-
(2007)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 252-253
-
-
Chang, L.1
Nakamura, Y.2
Montoye, R.K.3
Sawada, J.4
Martin, A.K.5
Kinoshita, K.6
Gebara, F.7
Agarwal, K.8
Acharyya, D.9
Haensch, W.10
Hosokawa, K.11
Jamsek, D.12
-
10
-
-
0023437909
-
Static noise margin analysis of MOS SRAM cells
-
Oct
-
E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
-
(1987)
IEEE J. Solid-state Circuits
, vol.SC-22
, Issue.5
, pp. 748-754
-
-
Seevinck, E.1
List, F.2
Lohstroh, J.3
-
11
-
-
77957975231
-
Dynamic SRAM stability characterization in 45 nm CMOS
-
S. O. Toh, Z. Guo, and B. Nikolic, "Dynamic SRAM stability characterization in 45 nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, 2010, pp. 35-36.
-
(2010)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 35-36
-
-
Toh, S.O.1
Guo, Z.2
Nikolic, B.3
-
12
-
-
58049102639
-
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis
-
M. Yamaoka, K. Osada, and T. Kawahara, "A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis," in Proc. ESSCIRC, 2008, pp. 286-289.
-
(2008)
Proc. ESSCIRC
, pp. 286-289
-
-
Yamaoka, M.1
Osada, K.2
Kawahara, T.3
-
13
-
-
63449132966
-
2 cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme
-
2 cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme," IEEE Trans. Syst. Sci. Cybern., vol. 44, no. 4, pp. 1192-1198, 2009.
-
(2009)
IEEE Trans. Syst. Sci. Cybern.
, vol.44
, Issue.4
, pp. 1192-1198
-
-
Kushida, K.1
Suzuki, A.2
Fukano, G.3
Kawasumi, A.4
Hirabayashi, O.5
Takeyama, Y.6
Sasaki, T.7
Katayama, A.8
Fujimura, Y.9
Yabe, T.10
-
14
-
-
84655165797
-
The effect of random dopant fluctuations on logic timing at low voltage
-
preprint
-
R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, and A. Chandrakasan, "The effect of random dopant fluctuations on logic timing at low voltage," IEEE Trans. VLSI Syst., pp. 1-14, 2011, preprint.
-
(2011)
IEEE Trans. VLSI Syst.
, pp. 1-14
-
-
Rithe, R.1
Chou, S.2
Gu, J.3
Wang, A.4
Datla, S.5
Gammie, G.6
Buss, D.7
Chandrakasan, A.8
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