Analysis of process-geometry modulations through 3D TCAD

2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Volumn , Issue , 2007, Pages 385-388

  Sponton, L ^a   Bomholt, L ^b   Fichtner, W ^a,b  

^a ETH ZURICH   (Switzerland)

^b SYNOPSYS SWITZERLAND LLC   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN OF EXPERIMENTS; ELECTRONIC DESIGN AUTOMATION;

65-NM TECHNOLOGIES; CRITICAL PROCESS PARAMETERS; DEVICE SIMULATIONS; FULL FACTORIAL DESIGN; PROCESS GEOMETRIES; PROCESS PARAMETERS; PROCESS VARIATION; SCREENING EXPERIMENTS;

SEMICONDUCTOR DEVICES;

EID: 84871956924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-211-72861-1_93     Document Type: Conference Paper

References (6)

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2. N. Rankin et al., "Statistical Spice Analysis of a 0.18 μm CMOS Digital/Analog Technology During Process Development,", Proc. of 2001 Int. Conference on Microelectronics Test Structures, pp. 19-23,2001
3. P. Vandervoorn et al., "CMOS Shallow-Trench-Isolation to 50-nm Channel Widths,". IEEE Trans. on El. Dev., Vol. 47, pp. 1175-1182, 2000.
4. C. Pacha et al, "Impact of STl-Induced Stress, Inverse Narrow Width Effect and Statistical Vth Variation on Leakage Currents in 120 nm CMOS,". Proc. of ESSDERC. pp. 397-400, 2004.
5. Synopsys Inc., "Sentaurus Process User's Manual", release Z-2007.03, 2007
6. G. Paasch and H. Übensee, "A Modified Local Density Approximation: Electron Density in Inversion Layers,", Physica Status Solidi (b). Vol. 113, pp. 165-178, 1982.