Flexible nano-floating-gate memory with channels of enhancement-mode Si nanowires

IEEE Transactions on Electron Devices

Volumn 59, Issue 11, 2012, Pages 2939-2942

  Jeon, Youngin ^a   Lee, Myeongwon ^a   Moon, Taeho ^a   Kim, Sangsig ^a  

^a Korea University   (South Korea)

Author keywords

Field effect transistor (FET); memory; nanocrystal (NC); nonvolatile; plastic substrate; Pt; silicon nanowire (Si NW) array; top down approach

Indexed keywords

A-STABILITY; BENDING CYCLES; ELECTRICAL CHARACTERISTIC; ENHANCEMENT-MODE; FLOATING-GATES; MECHANICAL FLEXIBILITY; NON-VOLATILE; NON-VOLATILE MEMORIES; ON-CURRENTS; PLASTIC SUBSTRATES; RETENTION TIME; SI NANOWIRE; SILICON NANOWIRES; SUBTHRESHOLD SWING; THRESHOLD VOLTAGE SHIFTS; TOP-DOWN APPROACH;

DATA STORAGE EQUIPMENT; FIELD EFFECT TRANSISTORS; FLEXIBLE ELECTRONICS; NANOCRYSTALS; NANOWIRES; PLATINUM;

SILICON;

EID: 84867900822     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2211879     Document Type: Article

References (26)

1. T. Moon, J. Kang, Y. Han, C. Kim, Y. Jeon, H. Kim, and S. Kim, "Si-based flexible memristive systems constructed using top-down methods," ACS Appl. Mater. Interfaces, vol. 3, no. 10, pp. 3957-3961, Sep. 2011.
2. H. I. Hanafi, S. Tiwari, and I. Khan, "Fast and long retention-time nanocrystal memory," IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1553-1558, Sep. 1996.
3. S. J. Baik, S. Choi, U.-I. Chung, and J. T. Moon, "High speed and nonvolatile Si nanocrystal memory for scaled Flash technology using highly field-sensitive tunnel barrier," in IEDM Tech. Dig., 2003, pp. 22.3.1-22.3.4.
4. R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. G. H. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, K.-M. Chang, and B. E. White, Jr., "A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory," in IEDM Tech. Dig., 2003, pp. 26.2.1-26.2.4.
5. T. B. Singh, N. Marjanovic, G. J. Matt, N. S. Sariciftci, R. Schwodiauer, and S. Bauer, "Nonvolatile organic field-effect transistor memory element with a polymeric gate electret," Appl. Phys. Lett., vol. 85, no. 22, pp. 5409-5411, Oct. 2004.
6. S.-J. Park and J.-S. Lee, "Flexible organic transistor memory devices," Nano Lett., vol. 10, no. 8, pp. 2884-2890, Jun. 2010.
7. K.-J. Baeg, D. Khim, D.-Y. Kim, S.-W. Jung, J. Koo, and Y.-Y. Noh, "Organic nano-floating-gate memory with polymer: [6, 6]-phenyl-C61 butyric acid methyl ester composite films," Jpn. J. Appl. Phys., vol. 49, no. 5, pp. 05EB01-1-05EB01-5, May 2010.
8. M. C. McAlpine, R. S. Friedman, S. Jin, K. h. Lin, W. U. Wang, and C. M. Lieber, "High-performance nanowire electronics and photonics on glass and plastic substrates," Nano Lett., vol. 3, no. 11, pp. 1531-1535, Sep. 2003.
9. A. J. Baca, J. H. Ahn, Y. Sun, M. A. Meitl, E. Menard, H. S. Kim, W. M. Choi, D. H. Kim, Y. Huang, and J. A. Rogers, "Semiconductor wires and ribbons for high performance flexible electronics," Angew. Chem. Int. Ed., vol. 47, no. 30, pp. 5524-5543, Jan. 2008.
10. M. C. McAlpine, R. S. Friedman, and C. M. Lieber, "High-performance nanowire electronics and photonics and nanoscale patterning on flexible plastic substrates," Proc. IEEE, vol. 93, no. 7, pp. 1357-1363, Jul. 2005.
11. J. Y. Yu, S. W. Chung, and J. R. Heath, "Silicon nanowires: Preparation, device fabrication transport properties," J. Phys. Chem. B, vol. 104, no. 50, pp. 11864-11870, Nov. 2000.
12. Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, "High performance silicon nanowire field effect transistors," Nano Lett., vol. 3, no. 2, pp. 149-152, Jan. 2003.
13. Y. Sun, H. Y. Yu, N. Singh, N. S. Shen, G. Q. Lo, and D. L. Kwong, "Multibit programmable Flash memory realized on vertical Si nanowire channel," IEEE Electron Device Lett., vol. 31, no. 5, pp. 390-392, May 2010.
14. M. Lee, Y. Jeon, T. Moon, and S. Kim, "Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS inverters on plastic," ACS Nano, vol. 5, no. 4, pp. 2629-2636, Feb. 2011.
15. E.-A. Chung, J. Koo, M. Lee, D.-Y. Jeong, and S. Kim, "Enhancementmode silicon nanowire field-effect transistors on plastic substrates," Small, vol. 5, no. 16, pp. 1821-1824, Aug. 2009.
16. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, "Metal nanocrystal memories Part II: Device characteristics," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1614-1622, Sep. 2002.
17. M. Takata, S. Kondoh, T. Sakaguchi, H. Choi, J.-C. Shim, H. Kurino, andM. Koyanagi, "New non-volatile memory with extremely high density metal nano-dots," in IEDM Tech. Dig., 2003, pp. 22.5.1-22.5.4.
18. C. Lee, A. Gorur-Seetharam, and E. C. Kan, "Operational and reliability comparison of discrete-storage nonvolatile memories: Advantages of single-and double-layer metal nanocrystals," in IEDM Tech. Dig., 2003, pp. 22.6.1-22.6.4.
19. J. J. Lee and D.-L. Kwong, "Metal nanocrystal memory with high-κ tunneling barrier for improved data retention," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 507-511, Apr. 2005.
20. D. Yeom, J. Kang, M. Lee, J. Jang, J. Yun, D.-Y. Jeong, C. Yoon, J. Koo, and S. Kim, "ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al2O3 gate oxides," Nanotechnology, vol. 19, no. 39, p. 395 204, Oct. 2008.
21. A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energyefficient electronic switches," Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011.
22. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, "Metal nanocrystal memories, Part I: Device design and fabrication," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, Sep. 2002.
23. I. Stievano, "Flash memories," InTech, pp. 177-196, Sep. 2011, 978-953-307-272-2.
24. M. Chen, H. Y. Yu, N. Singh, Y. Sun, N. S. Shen, X. Yuan, G.-Q. Lo, and D. L. Kwong, "Vertical-Si-nanowire SONOS memory for ultrahigh-density application," IEEE Electron Device Lett., vol. 30, no. 8, pp. 879-881, Aug. 2009.
25. S. J. Choi, D. I. Moon, J. P. Duarte, S. Kim, and Y. K. Choi, "A novel junctionless all-around-gate SONOS device with a quantum nanowire on a bulk substrate for 3D stack NAND Flash memory," in Proc. VLSIT, 2011, pp. 74-75.
26. J. Choi, K. Cho, and S. Kim, "Strain effects on optoelectronic characteristics of laterally arrayed silicon nanowires on a flexible substrate," Jpn. J. Appl. Phys., vol. 50, no. 1, pp. 01BH02-1-01BH02-4, Jan. 2011.