Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 293-304

  Chaudhuri, Mainak ^a   Gaur, Jayesh ^b   Bashyam, Nithiyanandan ^b   Subramoney, Sreenivas ^b   Nuzman, Joseph ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

^c INTEL CORPORATION   (Israel)

Author keywords

Bypass algorithm; Last level caches; Replacement policy

Indexed keywords

ACCESS PATTERNS; AVERAGE THROUGHPUT; CACHE HIERARCHIES; DATA TRANSACTION; EFFECTIVE ALGORITHMS; HARD COPIES; INTERVAL PREDICTION; L2 CACHE; LAST-LEVEL CACHES; PARALLEL EXECUTIONS; REPLACEMENT ALGORITHM; REPLACEMENT POLICY; SHARED MEMORIES; SINGLE-THREADED; THREE-LEVEL;

CACHE MEMORY; PARALLEL ARCHITECTURES; PROFITABILITY;

ALGORITHMS;

EID: 84867490427     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370860     Document Type: Conference Paper

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