Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 334-337

  Suzuki, Daisuke ^a   Natsui, Masanori ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; ASYMMETRIC CHARACTERISTIC; CIRCUIT DESIGNS; COMPACT LOOK-UP TABLES; CURRENT SWITCHING; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE; NONVOLATILE FPGA; SILICON AREA; SMALL FEATURES; SWITCHING CURRENTS; TRANSISTOR SIZE; TRANSISTOR SIZING;

MAGNETIC DEVICES; MOS DEVICES; TRANSISTORS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 84867315539     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2012.6292025     Document Type: Conference Paper

References (18)

1. I. Kuon, R. Tessier, and J. Rose, "FPGA architecture: survey and challenges," Foundation and Trends in Electronic Design Automation, vol. 2, no.2, pp. 135-253, 2007.
2. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no.2, pp. 203-215, Feb. 2007.
3. E. Pop, "Energy dissipation and transport in nanoscale devices," Nano Research, vol.3, no.3, pp. 147-169, Mar. 2010.
4. S. Masui et al., "A ferroelectric memory-based secure dynamically programmable gate array," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 715-725, May. 2003.
5. C.-Y. Wen et al., "A non-volatile look-up table design using PCM (phase-change memory) cells," IEEE Symp. VLSI Circuits, Dig. Tech. Papers, pp. 302-303, Jun. 2011.
6. Y. Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, "Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory," IEEE Int. Conf. Solid-State Circuits Dig. Tech. Papers, pp. 406-407, Feb. 2012.
7. W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny, "Evaluation of a non-volatile FPGA based on MRAM technology," Proc. IEEE Int. Conf. Integrated Circuit Design and Technology (ICICDT), pp. 1-4, May 2006.
8. W. Zhao, E. Belhaire, C. Chappert, F. Jacquet and P. Mazoyer, "New non-volatile logic based on spin-MTJ", Phys. Status SOLIDI A, vol. 205, no. 6, pp. 1373-1377, May 2008.
9. D. Suzuki et al., "Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate powerup field programmable gate array," IEEE Symp. VLSI Circuits, Dig. Tech. Papers, pp. 80-81, Jun. 2009.
10. D. Suzuki, M. Natsui, H. Ohno, and T. Hanyu, "Design of a process-variation-aware nonvolatile MTJ-based lookup-table circuit," Ext. Abstr. Solid State Devices and Materials (SSDM), pp.1146-1147, Sep. 2010.
11. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions," J. Appl. Phys., vol. 111, no. 7, p. 07E318 (2012).
12. S. Ikeda et al., "Magnetic tunnel junctions for spintronic memories and beyond," IEEE Trans. Electron Devices, vol.54, no.05, pp. 991-1002, May 2007.
13. T. Kawahara et al., "2 Mb SPRAM (spin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 109-120, Jan. 2008.
14. C. Yoshida et al., "Demonstration of non-volatile working memory through interface engineering in STT-MRAM," IEEE Symp. VLSI Technology, Dig. Tech. Papers, pp. 59-60, Jun. 2012.
15. W. Zhu, H. Li, Y. Chen, and X. Wang, "Current switching in MgO-Based magnetic tunneling junctions," IEEE Trans. Magn., vol. 47, no.1, pp. 156-120, Jan. 2011.
16. N. Sakimura et al., "High-speed simulator including accurate MTJ models for spintronics circuit design," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 1971-1974, May 2012.
17. S. Patil and D. J. Lilja, "A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions," Proc. ACM Great Lakes Symp. VLSI (GLSVLSI), pp. 7-12, May 2011.
18. X. Guo, E. Ipeak, and T. Soyata, "Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing," ACM Int. Symp. Computer and Architecture, pp. 371-382, Jun. 2010.