Fast, efficient floating-point adders and multipliers for FPGAs

ACM Transactions on Reconfigurable Technology and Systems

Volumn 3, Issue 3, 2010, Pages

  Hemmert, K Scott ^a   Underwood, Keith D ^b  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Design; Performance

Indexed keywords

AREA REQUIREMENT; CLOCK SPEED; DESIGN SPACES; DOUBLE PRECISION; FLOATING POINT UNITS; FLOATING-POINT ADDER; FLOATINGPOINT; FPGA DESIGN; FPGA TECHNOLOGY; IEEE-754 STANDARD; LIMITED PARALLELISM; PERFORMANCE; SPEED GRADES; VLSI DESIGN;

DESIGN; DIGITAL ARITHMETIC; OPTIMIZATION;

ADDERS;

EID: 84866919831     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1839480.1839481     Document Type: Article

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