Tradeoffs of designing floating-point division and square root on Virtex FPGAs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 195-203

  Wang, Xiaojun ^a   Nelson, B E ^a  

^a NONE

Author keywords

Field programmable gate arrays

Indexed keywords

COMMERCE; COMPUTERS; COSTS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT DESIGN; ITERATIVE METHODS; LOGIC GATES; PROGRAM PROCESSORS; SIGNAL RECEIVERS; THROUGHPUT;

DESIGN CONSIDERATIONS; FLOATING POINT DIVISIONS; FLOATING POINTS; FPGA(FIELD PROGRAMMABLE GATE ARRAY); HIGH THROUGHPUT; PIPELINED IMPLEMENTATION; SQUARE-ROOT ALGORITHMS; SQUARE-ROOT OPERATIONS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84942904204     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227255     Document Type: Conference Paper

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