A CAD suite for high-performance FPGA design

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 12-24

  Hutchings, Brad ^a   Bellows, Peter ^a   Hawkins, Joseph ^a   Hemmert, Scott ^a   Nelson, Brent ^a   Rytting, Mike ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TARGET RECOGNITION; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM DEBUGGING; RESPONSE TIME (COMPUTER SYSTEMS); USER INTERFACES;

GRAPHICAL DEBUGGING TOOL; RUN TIME RECONFIGURED DESIGN; SCHEMATIC GENERATOR;

COMPUTER AIDED LOGIC DESIGN;

EID: 0033488532     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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