On the design of fast IEEE floating-point adders

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2001, Pages 184-194

  Seidel, P M ^a   Even, G ^a  

^a Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; FORMAL LOGIC; OPTIMIZATION;

FLOATING-POINT ADDERS;

ADDERS;

EID: 0034870484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

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4. IEEE compliant floating-point adder that confirms with the pipelined packet-forwarding paradigm
5. The SNAP project: Design of floating point arithmetic units
6. Floating point adder/subtractor performing IEEE rounding and addition/subtraction in parallel
7. How many logic levels does floating-point addition require?
8. A reduced-area scheme for carry-select adders