A library of parameterizable floating-point cores for FPGAs and their application to scientific computing

Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05

Volumn , Issue , 2005, Pages 137-145

  Govindu, Gokul ^a   Scrofano, Ronald ^b   Prasanna, Viktor K ^a  

^a Department of Electrical Engineering ^*  (United States)

^b University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING-POINT ARITHMETICS; HIGH PRECISION; IEEE STANDARD 754; LENNARD-JONES FORCES; MOLECULAR-DYNAMICS SIMULATIONS; PARAMETERIZED; RECONFIGURABLE COMPUTING; SCIENTIFIC APPLICATIONS; SCIENTIFIC COMPUTING;

APPLICATIONS; DYNAMICS; MOLECULAR DYNAMICS; REGULATORY COMPLIANCE; STANDARDS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 60749122141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. Xilinx Inc., http://www.xilinx.com.
2. SRC Computers, Inc., http://www.srccomputers.com.
3. Cray, Inc., http://www.cray.com.
4. IEEE Standard for Binary Floating-Point Arithmetic, 1985, IEEE Std. 754-1985.
5. B. Fagin and C. Renard, "Field programmable gate arrays and floating point arithmetic," IEEE Transactions on VLSI Systems, vol. 2, no. 3, pp. 365-367, September 1994.
6. L. Louca, T. A. Cook, and W. H. Johnson, "Implementation of IEEE single precision floating point addition and multiplication on FPGAs," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, April 1996.
7. W. B. Ligon. III, S. McMillan, G. Monn, K. Schoonover, F. Stivers, and K. D. Underwood, "A re-evaluation of the practicality of floatingpoint operations on FPGAs," in Proceedings of the 6th Annual IEEE Svmposium on Field-Programmable Custom Computing Machines, April 1998.
8. P. Belanovic and M. Leeser, "A library of parameterized floating point modules and their use," in Proceedings of the 12th International Conference on Field Programmable Logic and Applications, M. Glesner, P. Zipf, and M. Renovell, Eds. Berlin: Springer-Verlag, September 2002, pp. 657-666.
9. X. Wang, M. Leeser, and H. Yu. "A parameterized floating-point library applied to multispectral image clustering," in Proceedings of the 7th annual MAPLD International Conference, September 2004, http://klabs.org/mapld04/abstracts/wang.x-a.pdf (abstract).
10. G. Lienhart, A. Kugel, and R. Manner, "Using floating-point arithmetic on FPGAs to accelerate scientific N-body simulations," in Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE Computer Society Press, April 2002, pp. 182-191.
11. J. Liang, R. Tessier, and O. Mencer, "Floating point unit generation and evaluation for FPGAs," in Proceedings of the 11th Annual IEEE Svmposium on Field-Programmable Custom Computing Machines, April 2003, pp. 185-194.
12. G. Govindu and V. K. Prasanna, "Analysis of high performance floating point arithmetic on FPGAs," in Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), April 2004.
13. L. Zhuo and V. K. Prasanna, "Scalable modular algorithms for floatingpoint matrix multiplication on FPGAs." in Proceedings of the 11th Reconfigurable Architectures Worksliop (RAW 2004), April 2004.
14. V. Daga, G. Govindu, V. K. Prasanna, S. Gangadharpalli, and V. Sridhar, "Floating-point based block LU decomposition on FPGAs," in Proceedings of the 2004 International Conference on Engineering Reconfigurable Systems and Algorithms, T. Plaks, Ed., June 2004, pp. 276-279.
15. R. Scrofano and V. K. Prasanna, "Computing Lennard-Jones potentials and forces with reconfigurable hardware," in Proceedings of the lnterational Conference on Engineering Reconfigurable Systems and Algorithms, T. Plaks, Ed., June 2004, pp. 284-290.
16. K. Underwood, "FPGAs vs. CPUs: Trends in peak floating-point performance," in Proceedings of the 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, February 2004.
17. K. D. Underwood and K. S. Hemmert, "Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance," in Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. April 2004.
18. D. Gay and T. Sumner, "paranoia (C version)," http://www.netlib.org/paranoia/.
19. ModelSim, http://www.model.com/.
20. M. D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand, "Reciprocation, square root, inverse square root, and some elementary functions using small multipliers," IEEE Transactions on Computers, vol. 49, no. 7, pp. 628-637, July 2000.
21. Y. Li and W. Chu, "A new non-restoring square root algorithm and its VLSI implementations," in Proceedings of the 1996 International Conference on Computer Design, October 1996.
22. M. Allen and D. Tildeseley, Computer Simulation of Liquids. New York: Oxford University Press, 1987.
23. N. Tredennick and B. Shimamoto, "Reconfigurable systems emerge," in Proceedings of the 2004 International Conference on Field Programmalbe Logic and Its Applications, ser. Lecture Notes in Computer Science, J. Becker, M. Platzner, and S. Vernalde, Eds., vol. 3203, September 2004, pp. 2-11.
24. Nallatech, http://www.nallatech.com.
25. Quixilica, http://www.quixilica.com.
26. M. D. Ercegovac and T. Lang, Digital Arithmetic. San Francisco: Morgan Kaufman, 2004.
27. J. F. Wakerly, Digital Design: Principles and Practices, 3rd ed. Prentice Hall, 2001.