FPU implementations with denormalized numbers

IEEE Transactions on Computers

Volumn 54, Issue 7, 2005, Pages 825-836

  Schwarz, Eric M ^a   Schmookler, Martin ^a   Trong, Son Dao ^b  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

Denormalized numbers; Floating point hardware; IEEE 754 Standard; Subnormals; Underflow trap

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSTRAINT THEORY; NUMBER THEORY;

DENORMALIZED NUMBERS; FLOATING POINT HARDWARE; SUBNORMALS; UNDERFLOW TRAP;

DIGITAL ARITHMETIC;

EID: 22944440034     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.118     Document Type: Article

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