1-GHz HAL SPARC64® dual floating point unit with RAS features

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2001, Pages 173-183

  Naini, A ^a   Dhablania, A ^a   James, W ^a   Das Sarma, D ^a  

^a HaL Computer Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CHARGED PARTICLES; CMOS INTEGRATED CIRCUITS; COMPUTER GRAPHICS; DATA TRANSFER; ERROR CORRECTION; ERROR DETECTION; MULTIPLYING CIRCUITS; SERVERS;

FLOATING POINT UNITS (FPU);

DIGITAL ARITHMETIC;

EID: 0034866186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Visual instruction set users guide
2. Reduced latency IEEE floating-point standard adder architectures
3. Leading-zero anticipator (LZA) in the IBM RISC system/6000 floating-point execution unit
4. Leading-zero anticipatory logic for high-speed floating point addition
5. IEEE standard for binary floating-point arithmetic
6. A signed multiplication technique
7. A suggestion for parallel multipliers
8. 167 MHz radix-4 floating point multiplier
9. Rounding algorithms for IEEE multipliers
10. Some properties of iterative square-rooting methods using high speed multiplication
11. Measuring the accuracy of ROM reciprocal tables
12. Rounding for quadratically converging algorithms for division and square root
13. Division algorithms and implementations