Implementation of IEEE single precision floating point addition and multiplication on FPGAs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1996, Pages 107-116

  Louca, Louca,s ^a   Cook, Todd A ^a   Johnson, William H ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER ARCHITECTURE; LOGIC GATES; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS;

COMPUTER ARITHMETIC; CUSTOM COMPUTING MACHINES; DIGIT SERIAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DIGITAL ARITHMETIC;

EID: 0030396384     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/fpga.1996.564761     Document Type: Conference Paper

References (6)