Miss-correlation folding: Encoding per-block miss correlations in compressed DRAM for data prefetching

Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium, IPDPS 2012

Volumn , Issue , 2012, Pages 691-702

  Liu, Gang ^a   Peir, Jih Kwon ^a   Lee, Victor ^b  

^a University of Florida   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

cache; compress; data parallel; miss correlation; prefetch; spatial; temporal

Indexed keywords

CACHE; COMPRESS; DATA PARALLEL; PREFETCHES; SPATIAL; TEMPORAL;

DISTRIBUTED PARAMETER NETWORKS; METADATA;

DATA COMPRESSION;

EID: 84866864300     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2012.68     Document Type: Conference Paper

References (54)

1. B. Abali, H. Franke, X. Shen, D. E. Poff, and T. B. Smith, "Performance of Hardware Compressed Main Memory," in 7th HPCA, 2001.
2. A.-R. Adl-Tabatabai, A. M. Ghuloum, and S. O. Kanaujia, "Compression in cache design," in 21st ACM International Conference on Supercomputing, 2007.
3. A. R. Alameldeen, and D. A. Wood, "Interactions between compression and prefetching in chip multiprocessors," in 13th HPCA, 2007.
4. M. Chamey, and A. Reeves, Generalized correlation based hardware prefetching, Technical Report EE-CEG-95-1, Cornell University, 1995.
5. T.-F. Chen, and J.-L. Baer, "Reducing memory latency via non-blocking and prefetching caches," in 5th ASPLOS, 1992.
6. T. M. Chilimbi, and M. Hirzel, "Dynamic hot data stream prefetching for general-purpose programs," in PLDI, 2002.
7. Y. Chou, "Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications," in 40th Micro, 2007.
8. K. Curewitz, P. Krishnan, and J. Vitter, "Practical prefetching via data compression," ACM SIGMOD Record, vol. 22, no. 2, pp. 266, 1993.
9. P. Diaz, and M. Cintra, "Stream chaining: Exploiting multiple levels of correlation in data prefetching," in 36th ISCA, 2009.
10. M. Ekman, and P. Stenstrom, "A Robust Main-Memory Compression Scheme," in 32nd ISCA, 2005.
11. M. Ferdman, and B. Falsafi, "Last-touch correlated data streaming," in ISPASS, 2007.
12. FeS2: A Full-system Execution-driven Simulator for x86, http://fes2.cs.uiuc.edu/.
13. J. Fu, J. H. Patel, and B. L. Janssens, "Stride directed prefetching in scalar processors," in 25th MICRO, 1992.
14. Z. Hu, M. Martonosi, and S. Kaxiras, "TCP: Tag Correlating Prefetchers," in 9th HPCA, 2003.
15. J. Huh, D. Burger, and S. W. Keckler, "Exploring the design space of future CMPs," in PACT, 2001.
16. D. Joseph, and D. Grunwald, "Prefetching using Markov predictors," in 24th ISCA, 1997.
17. N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers," in 17th ISCA, 1990.
18. G. B. Kandiraju, and A. Sivasubramaniam, "Going the distance for TLB prefetching: An application-driven study," in 29th ISCA, 2002.
19. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable DRAM alternative," in 36th ISCA, 2009.
20. J.-S. Lee, W.-K. Hong, and S.-D. Kim, "Design and evaluation of a selective compressed memory system," in IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1999.
21. V. Lee, C. Kim, J. Chhugani, M. Deisher, D. Kim et al., "Debunking the 100x GPU vs. CPU Myth: An Evaluation of Throughput Computing on CPU and GPU," in 37th ISCA, 2010.
22. V. Lee, Y. Chen, and P. Dubey, "Emerging Applications for Multi/Many-Core Processor," in 38th ISCA, 2011.
23. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hållberg et al., "Simics: A full system simulation platform," Computer, pp. 50-58, 2002.
24. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," ACM SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 92-99, 2005.
25. McCalpin, and J. D, "Memory Bandwidth and Machine Balance in Current High Performance Computers," IEEE Computer Society Technical Committee on Computer Architecture Newsletter, 1995.
26. K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith, "AC/DC: An adaptive data cache prefetcher," in 13th PACT, 2004.
27. K. J. Nesbit, and J. E. Smith, "Data cache prefetching using a Global History Buffer," in 10th HPCA, 2004.
28. OpenMP, http://www.openmp.org/.
29. Y. Qian, D. d'Humieres, and P. Lallemand, "Lattice BGK models for Navier-Stokes equation," EPL (Europhysics Letters), vol. 17, pp. 479, 1992.
30. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in 36th ISCA, 2009.
31. S. Raoux, G. Burr, M. Breitwisch, C. Rettner, Y. C. Chen et al., "Phase-change random access memory: A scalable technology," IBM Journal of Research and Development, vol. 52, no. 4.5, pp. 465-479, 2008.
32. Internal Report, "Single-Value Dynamic Encoding," unpublished.
33. N. Satish, M. Harris, and M. Garland, "Designing efficient sorting algorithms for manycore gpus," in IPDPS, 2009.
34. X. Shi, Z. Yang, J.-K. Peir, L. Peng, Y.-K. Chen et al., "Coterminous locality and coterminous group data prefetching on chip-multiprocessors," in 20th IPDPS, 2006.
35. Y. Solihin, J. Lee, and J. Torrellas, "Using a user-level memory thread for correlation prefetching," in 29th ISCA, 2002.
36. S. Somogyi, T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos, "Spatial memory streaming," in 33rd ISCA, 2006.
37. S. Somogyi, T. F. Wenisch, A. Ailamaki, and B. Falsafi, "Spatio-temporal memory streaming," in 36th ISCA, 2009.
38. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt, "Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers," in 13th HPCA, 2007.
39. J. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy, "POWER4 system microarchitecture," IBM Technical White Paper, Oct, 2001.
40. POSIX thread, https://computing.llnl.gov/tutorials/pthreads/.
41. R. Tremaine, P. Franaszek, J. Robinson, C. Schulz, T. Smith et al., "IBM memory expansion technology (MXT)," IBM Journal of Research and Development, vol. 45, no. 2, pp. 271-285, 2001.
42. J. S. Vitter, and P. Krishnan, "Optimal prefetching via data compression," in 32nd Annual Symposium on Foundations of Computer Science, 1991.
43. T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki et al., "Temporal Streaming of Shared Memory," in 32nd ISCA, 2005.
44. T. F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsafi, and A. Moshovos, "Temporal streams in commercial server applications," in IEEE International Symposium on Workload Characterization, 2008.
45. T. F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsafi, and A. Moshovos, "Practical off-chip meta-data for temporal memory streaming," in 15th HPCA, 2009.
46. P. R. Wilson, S. F. Kaplan, and Y. Smaragdakis, "The case for compressed caching in virtual memory systems," in Proceedings of USENIX Annual Technical Conference, 1999.
47. J. Yang, and R. Gupta, "Frequent value locality and its applications," ACM Trans. on Embedded Computing Systems, vol. 1, no. 1, pp. 79-105, 2002.
48. L. Yang, H. Lekatsas, and R. P. Dick, "High-performance operating system controlled memory compression," in 43rd ACM/IEEE Design Automation Conference, 2006.
49. M. T. Yourst, "PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator," in ISPASS, 2007.
50. Y. Zhang, J. Yang, and R. Gupta, "Frequent value locality and value-centric data cache design," in 9th ASPLOS, 2000.
51. Y. Zhang, and R. Gupta, "Enabling partial cache line prefetching through data compression," in International Conference on Parallel Processing, 2003.
52. C. Zilles, "Benchmark health considered harmful," ACM SIGARCH Computer Architecture News, vol. 29, no. 3, pp. 4-5, 2001.
53. J. Ziv, and A. Lempel, "A universal algorithm for sequential data compression," IEEE Transactions on Information Theory, vol. 23, no. 3, pp. 337-343, 1977.
54. J. Ziv, and A. Lempel, "Compression of individual sequences via variable-rate coding," IEEE Transactions on Information Theory, vol. 24, no. 5, pp. 530-536, 1978.