Compression in cache design

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2007, Pages 190-201

  Adl Tabatabai, Ali Reza ^a   Ghuloum, Anwar M ^a   Kanaujia, Shobhit O ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Cache compression; Cache design; Prefetching

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER SIMULATION; SYSTEMS ANALYSIS;

CACHE COMPRESSION; CACHE DESIGN; COMPANION LINE PREFETCHING (CLP); PREFETCHING;

DATA COMPRESSION;

EID: 34548034460     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1274971.1274999     Document Type: Conference Paper

References (24)

1. http://www.itrs.net/Common/2004Update/2004Update.htm International Technology Roadmap for Semiconductors, 2004 update. Semiconductor Industry Association, 2004.
2. http://www.intel.com/products/processor/itanium2/index.htm , Intel® Itanium® 2 Processor.
3. th Annual International Symposium, on Computer Architecture, pages 388-397, 1990.
4. th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 51-61, Boston, Massachusetts, October 1992, ACM.
5. th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222-233, Cambridge, Massachusetts, October 1996, ACM.
6. th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 115-126, San Jose, California, October 1998, ACM.
7. Wilson P., Kaplan S., Smaragdakis Y, "The Case for Compressed Caching in Virtual Memory Systems", USENIX Annual Technical Conference, 1999.
8. Tremaine R., Fanaszek P., Robinson J., Schulz C., Smith T.,Wazlowski, M., and Bland, P., "IBM Memory Expansion Technology (MXT)", in IBM Journal of Research and Development, Vol. 45, No. 2, March 2001.
9. Lee, J.-S., Hong, W.-K., Kim, S.-D, "Design and Evaluation of a Selective Compressed Memory System", In Proceedings of the IEEE International Conference on Computer Aided Design, VLSI in Computers and Processors, Austin, 1999.
10. Yang J., Zhang Y., Gupta R., "Frequent value locality and value-centric data cache", In proceedings of the ninth international conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, 2000.
11. rd annual ACM/IEEE international symposium, on Microarchitecture, 2000.
12. nd Euromicro Conference, IEEE Computer Society Press, September 1996.
13. st Annual International Symposium on Computer Architecture, 2004.
14. E. Hallnor, S. Reinhardt "A Unified Compressed Memory Hierarchy", in Proc. 11th Int'l Symp. on High-Performance Computer Architecture (HPCA), February 2005.
15. nd annual International Symposium on Computer Architecture (ISCA), June 2005.
16. Singhal, R.; Venkatraman, K.S.; Cohn, E.; Holm, J.G.; Koufaty, D; Lin, M-J.; Madhav, M.; Mattwandel, M.; Nidhi, N.; Pearce, J.; Seshadri, M. "Performance Analysis and Validation of the Intel® Pentium.® 4 Processor on 90nm. Technology." Intel Technology Journal. http://developer.intel.com/technologv/itj/2004/volume08issu e01/(February 2004).
17. Gochman, S.; Ronen, R.; Anati, I.; Berkovits, A.; Kurts, T.; Naveh, A.; Saeed, A.;Sperber, Z.; and Valentine, R. "The Intel® Pentium® M Processor: Microarchitecture and Performance.", Intel Technology Journal, http://developer.intel.com/technotogy/itj/2003/volume07issu e02/ (May 2003).
18. A. Agarwal, J. Hennessy, and M. Horowitz, "Cache Performance of Operating System and Multiprogramming Workloads", ACM Transactions on Computer Systems, 6(4):393-431, November 1988.
19. A. Agarwal, S. Pudar, "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches", in proceedings of 20th International Symposium, on Computer Architecture, 1993: 179-190.
20. http://www.intel.com/products/server/processors/index.htm Intel Xeon Processor Family.
21. Y.Zhang and R. Gupta,"Enabling Partial Cache Line Prefetching Through Data Compression", International Conference on Parallel Processing, pages 277-285, Kaohsiung, Taiwan, October 2003
22. Gailly, J. and Adler, M., "Zlib general purpose compression library", User manual, for zlib version 1.0.4, URL: http://quest.jpl. nasa.gov/zlib/. July 1996
23. E. G. Hallnor and S. K. Reinhardt "Compressed Memory Hierarchy using an Indirect Index Cache", Proc. 3rd Workshop on Memory Performance Issues (WMPI), June 2004.
24. th International Symposium, on High-Performance Computer Architecture, 2007.