Characteristics of a novel compliant bump for 3-D stacking with high-density inter-chip connections

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 1, 2011, Pages 83-91

  Watanabe, N ^a   Asano, T ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

3 D integration; 3 D LSI; 3 D stacking; Compliant bump; compliant interconnection; cone bump; flip chip bonding; high density inter chip connections; metal oxide semiconductor field effect transistor (MOSFET) degradation; pyramid bump; room temperature bonding; undercut resist method

Indexed keywords

3-D INTEGRATION; 3-D LSI; 3-D STACKING; COMPLIANT BUMP; COMPLIANT INTERCONNECTION; FLIP-CHIP BONDING; INTER-CHIP; METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS; PYRAMID BUMP; ROOM TEMPERATURE; UNDERCUT RESIST METHOD;

BONDING; ELECTRIC BREAKDOWN; GOLD; INTERCONNECTION NETWORKS; PHOTORESISTS;

MOSFET DEVICES;

EID: 84866846495     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2010.2101450     Document Type: Article

References (25)

1. M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp. 17-22, Jul./Aug. 1998.
2. P. Morrow, B. Black, M. J. Kobrinsky, S. Muthukumar, D. Nelson, C. M. Park, and C. Webb, "Design and fabrication of 3D microprocessors," Mater. Res. Symp. Proc., vol. 970, 2007.
3. K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, and M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology," in Int. Electron Devices Meeting Technical Digest, 2000, pp. 165-168.
4. Y. Kurita, S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, C. Kakegawa, M. Kawano, Y. Egawa, Y. Saeki, H. Kikuchi, O. Kato, A. Yanagisawa, T. Mitsuhashi, M. Ishino, K. Shibata, S. Uchiyama, J. Yamada, and H. Ikeda, "A 3D stacked memory integrated on a logic device using SMAFTI technology," in Proc. Electron. Compon. Technol. Conf., 2007, pp. 821-829.
5. C. A. Bower,D.Malta, D. Temple, J. E. Robinson, P. R. Coffman, M. R. Skokan, and T. B. Welch, "High density vertical interconnects for 3-D integration of silicon integrated circuits," in Proc. Electron. Compon. Technol. Conf., 2006, pp. 399-403.
6. V. Suntharalingam, R. Berger, J. A. Burns, C. K. Chen, C. L. Keast, J. M. Knecht, R. D. Lambert, K. L. Newcomb, D. M. O'Mara, D. D. Rathman, D. C. Shaver, A. M. Soares, C. N. Stevenson, B. M. Tyrrell, K.Warner, B. D.Wheeler, D. R.W. Yost, and D. J. Young, "Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology," in Int. Solid-State Circuits Conf. Digest Tech. Papers, 2005, pp. 356-357.
7. H. Kurino, K. W. Lee, T. Nakamura, K. Sakuma, K. T. Park, N. Miyakawa, H. Shimazutsu, K. Y. Kim, K. Inamura, and M. Koyanagi, "Intelligent image sensor chip with three dimensional structure," in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 879-882.
8. M. Koyanagi, Y. Nakagawa, K. W. Lee, T. Nakamura, Y. Yamada, K. Inamura, K. T. Park, and H. Kurino, "Neuromorphic vision chip fabricated using three-dimensional integration technology," in Int. Solid-State Circuits Conf. Digest Tech. Papers, 2001, pp. 270-271.
9. K. Kameyama, Y. Okayama, M. Umemoto, A. Suzuki, H. Terao, M. Hoshino, and K. Takahashi, "Application of high reliable silicon thru-via to image sensor CSP," in Extended Abstracts Int. Conf. Solid State Devices Mater., 2004, pp. 276-277.
10. R. S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proc. IEEE, vol. 94, no. 6, pp. 1214-1224, Jun. 2006.
11. J. John, L. Zimmermann, P. D. Moor, and C. V. Hoof, "High-density hybrid interconnect methodologies," Nucl. Inst. Meth. A, vol. 531, no. 1-2, pp. 202-208, Sep. 2004.
12. S. Wakiyama, H. Ozaki, Y. Nabe, T. Kume, T. Ezaki, and T. Ogawa, "Novel low-temperature CoC interconnection technology for multichip LSI (MCL)," in Proc. Electron. Compon. Technol. Conf., 2007, pp. 610-615.
13. H. Huebner, O. Ehrmann, M. Eigner, W. Gruber, A. Klumpp, R. Merkel, P. Ramm, M. Roth, J. Weber, and R. Wieland, "Face-to-face chip integration with full metal interface," in Proc. Adv. Metallization Conf., 2002, pp. 53-58.
14. K. Tanida, M. Umemoto, N. Tanaka, Y. Tomita, and K. Takahashi, "Micro Cu bump interconnection on 3D chip stacking technology," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2264-2270, Apr. 2004.
15. K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, and M. Bonkohara, "Ultra-high-density interconnection technology of three-dimensional packaging," Microelectron. Reliab., vol. 43, no. 8, pp. 1267-1279, Aug. 2003.
16. K. N. Chen, A. Fan, and R. Reif, "Microstructure examination of copper wafer bonding," J. Electron. Mater., vol. 30, no. 4, pp. 331-335, Apr. 2001.
17. N. Tanaka, Y. Yoshimura, T. Naito, C. Miyazaki, Y. Nemoto, M. Nakanishi, and T. Akazawa, "Ultra-thin 3D-stacked SIP formed using room-temperature bonding between stacked chips," in Proc. Electron. Compon. Technol. Conf., 2005, pp. 788-794.
18. A. Shigetou, T. Itoh, and T. Suga, "Bumpless interconnect of ultrafine Cu electrodes by Surface Activated Bonding (SAB) method," Electron. Comm. Jpn. II, vol. 89, no. 12, pp. 34-42, Nov. 2006.
19. P. Enquist, "Direct Bond Interconnect (DBI)-Technology for scaleable 3D SoCs," in Proc. 3D Architectures Semiconductor Integration Packag., 2006.
20. N.Watanabe, Y. Ootani, and T. Asano, "Pyramid bumps for fine-pitch chip-stack interconnection," Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2751-2755, Apr. 2005.
21. N. Watanabe, T. Kojima, and T. Asano, "Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections," in Int. Electron Devices Meeting Tech. Digest, 2005, pp. 687-690.
22. N. Watanabe, T. Kojima, and T. Asano, "Wafer-level compliant bump for 3D chip-stacking," in Proc. Int. Symp. VLSI Technol., Syst., Appl., 2006, pp. 135-136.
23. N. Watanabe and T. Asano, "A large number of I/O connections using compliant bump," in Proc. Electron. Compon. Technol. Conf., 2006, pp. 125-130.
24. G. Dorda, "Piezoresistance in quantized conduction bands in silicon inversion layers," J. Appl. Phys., vol. 42, no. 5, pp. 2053-2060, Apr. 1971.
25. D. Colman, R. T. Bate, and J. P. Mize, "Mobility anisotropy and piezoresistance in silicon p-type inversion layers," J. Appl. Phys., vol. 39, no. 4, pp. 1923-1931, Mar. 1968.