Ultra-high-density interconnection technology of three-dimensional packaging

Microelectronics Reliability

Volumn 43, Issue 8, 2003, Pages 1267-1279

  Takahashi, Kenji ^a   Umemoto, Mitsuo ^a   Tanaka, Naotaka ^a,b   Tanida, Kazumasa ^a   Nemoto, Yoshihiko ^a   Tomita, Yoshihiro ^a   Tago, Masamoto ^a   Bonkohara, Manabu ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIFFUSION; MICROELECTRONICS; SEMICONDUCTOR MATERIALS; TIN; ULTRASONICS;

INTERCONNECTION TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 0042164578     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(03)00167-7     Document Type: Conference Paper

References (43)

1. Bonkohara M. Japan activities in 1999 electronic system-integration technology. In: 6th Ann KGD Industrial Workshop, Napa, CA, USA, September 1999.
2. Bonkohara M. J. Jpn. Inst. Electron Packaging. 4(3):2001;185-191. [in Japanese].
3. Al-sarawi S.F., Abbott D., Franzon P.D. A Review of 3-D packaging technology. IEEE Trans. Compon. Pack. Manuf. Technol. Part B. 21(1):1998;2-14.
4. Fujita K., Kimura T., Narai A., Sota Y., Miyata K., Matsune Y.et al. Stacked CSP (chip size package) technology. Sharp Tech. J. 71:1998;58-63. [in Japanese].
5. Yoshida A, Zoba D, Lee CH, Lee SG, Kim YH, Park SS, et al. An extremely thin, BGA format chip scale package and stacking. In: 2001 Int Conf Electron Packaging Proc, 2001 ICEP, Tokyo, Japan, April 2001. p. 44-7.
6. Heo YH, Yoshida A, Groover R. Advances in 3D packaging - trends and technologies for multi chip die and package stack. In: Proc 6th VLSI Packaging Workshop, Kyoto, Japan, November 2002. p. 125-9.
7. Carson J. 3D silicon and recognition based logic - enabling the road to HAL. In: Proc SPIE, vol. 4109, Critical technologies for the future computing, SPIE Int Symp Optical Science Technol, San Diego, CA, USA, August 2000. p. 264-70.
8. Kim YG. Folded stacked package development. In: Proc 52nd Electron Components Technology Conf, 52nd ECTC, San Diego, CA, USA, May 2002. p. 1341-6.
9. Imoto T, Matsui M, Takubo C, Akejima S, Kariya T, Nishikawa T, et al. Development of 3-dimensional module package - system block module. In: Proc 51st Electron Components Technol Conf, 51st ECTC, Orlando, FL, USA, May/June 2001. p. 552-7.
10. Uno T, Onodera H, Miyata K, Takashima A. Development of 3-dimensional type multi chip package which mounted 8 LSI chips. In: Proc 12th Microelectron Symp, MES 2002, Osaka, Japan, October 2002. p. 59-62 [in Japanese].
11. Matsumoto T, Kudoh Y, Tahara M, Yu KH, Miyakawa N, Itani H, et al. Three-dimensional integration technology based on wafer bonding technique using micro-bumps. In: Ext Abstr 1995 Int Conf Solid State Devices Materials, Osaka, Japan, August 1995. p. 1073-4.
12. Ramm P., Bollmann D., Braun R., Buchner R., Cao-Minh U., Engelhardt M.et al. Three dimensional metallization for vertically integrated circuits. Microelectron. Eng. 37-38:1997;39-47.
13. Lu J.Q., Kumar A., Kwon Y., Eisenbraun E.T., Kraft R.P., McDonald J.F.et al. 3-D integration using wafer bonding. Edelstein D., Dixit G., Yasuda Y., Ohba T. Advanced Metallization Conf 2000 (AMC 2000). 2001;515-521 Materials Research Society, Warrendale, PA, USA.
14. Sasaki K, Matsuo M, Hayasaka N, Okumura K. 128 Mbit NAND flash memory by chip-on-chip technology with Cu through plug. In: 2001 Int Conf Electron Packaging Proc, 2001 ICEP, Tokyo, Japan, April 2001. p. 39-43.
15. Suemasu T., Itoi K., Yamamoto S., Takizawa T. High aspect ratio through-hole interconnections in silicon substrates. Fujikura Gihou. 32:2002;53-57. [in Japanese].
16. Stuby KP, Falls W. Hourglass-shaped conductive connection through semiconductor structures. United States Patent 3,648,131, March 7, 1972.
17. Warabisako T. Stacked semiconductor integrated circuits and manufacturing method. Japan Patent S59-222954, December 12, 1983 [in Japanese].
18. Laermer F, Schilp A. Method of anisotropically etching silicon. United States Patent 5,501,893, March 26, 1996.
19. Sakai I, Sasaki K, Tomioka K, Ohiwa T, Sekine M, Miura T, et al. High rate deep Si etching. In: Proc Int Symp Dry Process, Tokyo, Japan, November 2001. p. 57-61.
20. Savastiouk S., Siniaguine O., DiOrio M. Moore's law: The next dimension. Adv. Packaging. 7:1998;55-58.
21. Takahashi K, Fujitsu T. In: 25th Nikkei Microdevices Jisso Seminar, Tokyo, Japan, May 1999 [in Japanese].
22. Klink G., Landesberger C., Feil M., Ansorge F., Aschenbrenner R. Ultra thin ICs open new dimensions for microelectronic systems. Adv. Microelectron. 27(4):2000;23-25.
23. Takahashi K., Terao H., Tomita Y., Yamaji Y., Hoshino M., Sato T.et al. Current status of research and development for three-dimensional chip stack technology. Jpn. J. Appl. Phys. 40(4B):2001;3032-3037.
24. Sakurai T. In: 31st Nikkei Microdevices Jisso Seminar, Tokyo, Japan, April 2000. p. 1-1-27 [in Japanese].
25. Shibata H. In: Tutorial Text Advanced Metallization Conf 2002 Asian Session, ADMETA 2002, Tokyo, Japan, October 2002. p. 113-36 [in Japanese].
26. Tomisaka M, Yonemura H, Hoshino M, Takahashi K. Electroplating Cu filling for through-vias for three-dimensional chip stacking. In: Proc 52nd Electron Components Technol Conf, 52nd ECTC, San Diego, CA, USA, May 2002. p. 1432-8.
27. Sunohara M, Fujii T, Hoshino M, Yonemura H, Tomisaka M, Takahashi K. Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI. In: Proc 52nd Electron Components Technol Conf, 52nd ECTC, San Diego, CA, USA, May 2002. p. 238-45.
28. Morifuji T, Tomita Y, Tanaka N, Sato T, Takahashi K. Flip-chip bonding technologies utilizing micro Au bumps in 20-μm-pitch. In: 8th Symp Microjoining Assembly Technol Electron, Mate 2002, Yokohama, Japan, January/February 2002. p. 119-24 [in Japanese].
29. Palm P., Määttänen J., Tuominenc A., Ristolainen E. Reliability of 80 μm pitch flip chip attachment on flex. Microelectron. Reliab. 41(5):2001;633-638.
30. Luk C.F., Chan Y.C., Hung K.C. Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies. Microelectron. Reliab. 42(3):2002;381-389.
31. Umemoto M, Tomita Y, Morifuji T, Ando T, Sato T, Takahashi K. Superfine flip-chip interconnection in 20-μm-pitch utilizing reliable microthin underfill technology for 3D stacked LSI. In: Proc 52nd Electron Components Technol Conf, 52nd ECTC, San Diego, CA, USA, May 2002. p. 1454-95.
32. Tanaka N, Sato T, Yamaji Y, Morifuji T, Umemoto M, Takahashi K. Mechanical effect of copper through-vias in a 3D die-stacked module. In: Proc 52nd Electron Components Technol Conf, 52nd ECTC, San Diego, CA, USA, May 2002. p. 473-9.
33. Kajiwara R, Koizumi M, Morita T, Nishimura A, Narisawa A, Shinoda M. Ultrasonic flip chip bonding technology for LSI chip with high pin counts. In: Proc 7th Symp Microjoining Assembly Techol Electron, Mate 2003, Yokohama, Japan, February 2001. p. 161-6 [in Japanese].
34. Kimura M, Iwasaki T, Yamada S, Hatanaka Y, Fujioka H, Ueda N. Ultrasonic flip-chip bonding technology using preformed underfill-resin. In: 2001 Int Conf Electron Packaging Proc, 2001 ICEP, Tokyo, Japan, April 2001. p. 253-8.
35. Tomioka T, Iguchi T, Mori I, Saito M. Thremosonic flip chip bonding for low cost packaging. In: 2002 Proc Int Symp Microelectron, 2002 IMAPS, Denver, CO, USA, September 2002. p. 360-5.
36. Natsuaki M, Watanabe M, Nomoto T, Ando F, Takashima A, Kobayashi H, et al. Flip-chip interconnection technology for fine-pitch device. In: Proc 9th Symp Microjoining Assembly Techol Electron, Mate 2003, Yokohama, Japan, February 2003. p. 17-20 [in Japanese].
37. Tanida K, Tomita Y, Morifuji T, Ando T, Kajiwara R, Tanaka N, et al. Superfine flip chip interconnections in 20-μm-pitch. In: 2002 Int Conf Electron Packaging Proc, 2002 ICEP, Tokyo, Japan, April 2002. p. 333-8.
38. Suga T, Otsuka K. Bump-less interconnections for next generation system packaging. In: Proc 51st Electron Components Technol Conf, 51st ECTC, Orlando, FL, USA, May/June 2001. p. 1003-8.
39. Tomita Y, Tago M, Nemoto Y, Takahashi K. Cu bump interconnections in 20 μm pitch utilizing electroless tin-cap on 3D stacked LSI. In: Proc Int Symp Electron Mater Packaging 2001, EMAP 2001, Jeju, Korea, November 2001. p. 107-14.
40. Nemoto Y, Tomita Y, Takahashi K. In: Proc 16th JIEP Ann Meeting, Yokohama, Japan, March 2002. p. 87-8 [in Japanese].
41. Tago M, Tomita Y, Sunohara M, Fujii T, Sato T, Takahashi K. In: Proc 16th JIEP Ann Meeting, Yokohama, Japan, March 2002. p. 307-8 [in Japanese].
42. Fister JC, Zarlingo SP. Solderbility performance of tin coated copper alloy strip for connector components. In: Proc 41st Electron Components Technol Conf, 41st ECTC, Atlanta, GA, USA, May 1991. p. 229-33.
43. Tomita Y, Tago M, Nemoto Y, Takahashi K. Copper bump bonding with electroless metal cap on 3-dimensional stacked structure. In: Proc 3rd Electron Packaging Technol Conf, 3rd EPTC, Singapore, December 2000. p. 286-91.