A large number of I/O connections using compliant bump

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 125-130

  Watanabe, Naoya ^a   Asano, Tanemasa ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; FAILURE (MECHANICAL); INTEGRATED CIRCUIT LAYOUT; SWITCHING;

COMPLIANT BUMP; SWITCH ARRAYS;

CHIP SCALE PACKAGES;

EID: 33845563312     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645635     Document Type: Conference Paper

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