Novel low-temperature CoC interconnection technology for Multichip LSI (MCL)

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 610-615

  Wakiyama, Satoru ^a   Ozaki, Hiroshi ^a   Nabe, Yoshihiro ^a   Kume, Tomomi ^a   Ezaki, Takayuki ^a   Ogawa, Tohru ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; ELECTRIC RESISTANCE; INTERMETALLICS;

CHIP ON CHIP (COC) INTERCONNECTION; SYSTEM ON CHIP (SOC); TEST ELEMENT GROUPS (TEG);

LSI CIRCUITS;

EID: 35348885430     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373859     Document Type: Conference Paper

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3. T. Ezaki et al., "A 160-Gb/s Interface Design Configuration for Multichip LSI", ISSCC Dig. Tech. Papers, pp. 140-141, Feb. 2004.
4. Naoya Watanabe and Tanemasa Asano, "A Large Number of I/O Connections Using Compliant Bump", Proceedings of ECTC 2005, pp. 125-130.
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