A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 261-264

  Hoppner, Sebastian ^a   Shao, Chenming ^a   Eisenreich, Holger ^a   Ellguth, Georg ^a   Ander, Mario ^a   Schuffny, Rene ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

DVFS; GALS; MPSoC

Indexed keywords

65NM CMOS TECHNOLOGY; DVFS; FAST SWITCHING; GALS; LEVEL CHANGE; MPSOC; ON-CHIP SUPPLY; PARASITICS; POWER MANAGEMENTS; PRE-CHARGE; SUPPLY LEVELS; SUPPLY NETWORKS; VOLTAGE DROP;

CMOS INTEGRATED CIRCUITS; ENERGY MANAGEMENT; MULTIPROCESSING SYSTEMS; NOISE ABATEMENT;

NETWORK ARCHITECTURE;

EID: 84866634622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2012.6271840     Document Type: Conference Paper

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