-
1
-
-
0000793139
-
Cramming more components onto integrated circuits
-
Apr.
-
G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, Apr. 1965.
-
(1965)
Electronics
, vol.38
, Issue.8
-
-
Moore, G.1
-
2
-
-
24944549727
-
Two heads are better than one
-
Sep.
-
W. Knight, "Two heads are better than one," IEE Rev., pp. 33-35, Sep. 2005.
-
(2005)
IEE Rev.
, pp. 33-35
-
-
Knight, W.1
-
3
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
DOI 10.1109/2.976921
-
L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, vol. 35, pp. 70-78, Jan. 2002. (Pubitemid 34069383)
-
(2002)
Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
4
-
-
0036505033
-
The raw microprocessor: A computational fabric for software circuits and general-purpose programs
-
DOI 10.1109/MM.2002.997877
-
M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffmann, P. Johnson, J. W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal, "The raw microprocessor: A computational fabric for software circuits and general purpose programs," IEEE Micro, vol. 22, no. 2, pp. 25-35, 2002. (Pubitemid 34434061)
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 25-35
-
-
Taylor, M.B.1
Kim, J.2
Miller, J.3
Wentzlaff, D.4
Ghodrat, F.5
Greenwald, B.6
Hoffman, H.7
Johnson, P.8
Lee, J.-W.9
Lee, W.10
Ma, A.11
Saraf, A.12
Seneski, M.13
Shnidman, N.14
Strumpen, V.15
Frank, M.16
Amarasinghe, S.17
Agarwal, A.18
-
5
-
-
0037669851
-
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
-
K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore, "Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture," in Proc. 30th Annual Int. Symp. Computer Architecture, 2003, pp. 422-433.
-
(2003)
Proc. 30th Annual Int. Symp. Computer Architecture
, pp. 422-433
-
-
Sankaralingam, K.1
Nagarajan, R.2
Liu, H.3
Kim, C.4
Huh, J.5
Burger, D.6
Keckler, S.W.7
Moore, C.R.8
-
7
-
-
36849022584
-
A 5-GHz mesh interconnect for a teraflops processor
-
DOI 10.1109/MM.2007.4378783
-
Y. Hoskote et al., "A 5-GHz mesh interconnect for a teraflops processor," IEEE Micro, vol. 27, no. 5, pp. 51-61, 2007. (Pubitemid 350218387)
-
(2007)
IEEE Micro
, vol.27
, Issue.5
, pp. 51-61
-
-
Hoskote, Y.1
Vangal, S.2
Singh, A.3
Borkar, N.4
Borkar, S.5
-
8
-
-
78650922410
-
A 48-Core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling
-
Jan.
-
J. Howard et al., "A 48-Core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 173-183, Jan. 2011.
-
(2011)
IEEE J. Solid-State Circuits
, vol.46
, Issue.1
, pp. 173-183
-
-
Howard, J.1
-
9
-
-
85008053864
-
An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS
-
S. Vangal et al., "An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, pp. 29-41, 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, pp. 29-41
-
-
Vangal, S.1
-
10
-
-
50249185641
-
A 45 nm logic technology with high k+metal gate transistors, strained silicon, 9Cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging
-
Dec.
-
K. Mistry et al., "A 45 nm logic technology with high k+metal gate transistors, strained silicon, 9Cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging," in IEDM Dig. Tech. Papers, Dec. 2007, pp. 247-250.
-
(2007)
IEDM Dig. Tech. Papers
, pp. 247-250
-
-
Mistry, K.1
-
11
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. 38th Design Automation Conf., 2001, pp. 681-689.
-
(2001)
Proc. 38th Design Automation Conf.
, pp. 681-689
-
-
Dally, W.J.1
Towles, B.2
-
12
-
-
0027306402
-
Symmetric crossbar arbiters for VLSI communication switches
-
Jan.
-
Y. Tamir and H.-C. Chi, "Symmetric crossbar arbiters for VLSI communication switches," IEEE Trans. Parallel Distrib. Syst., vol. 4, no. 1, pp. 13-27, Jan. 1993.
-
(1993)
IEEE Trans. Parallel Distrib. Syst.
, vol.4
, Issue.1
, pp. 13-27
-
-
Tamir, Y.1
Chi, H.-C.2
-
13
-
-
77957974226
-
A 2 Tb/s 6x4 mesh network with DVFS and 2.3 Tb/s/W router in 45 nm CMOS
-
P. Salihundam et al., "A 2 Tb/s 6x4 mesh network with DVFS and 2.3 Tb/s/W router in 45 nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, 2010, pp. 121-124.
-
(2010)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 121-124
-
-
Salihundam, P.1
-
14
-
-
0026825968
-
Virtual-channel flow control
-
Mar.
-
W. J. Dally, "Virtual-channel flow control," IEEE Trans. Parallel Distrib. Syst., vol. 3, no. 2, pp. 194-205, Mar. 1992.
-
(1992)
IEEE Trans. Parallel Distrib. Syst.
, vol.3
, Issue.2
, pp. 194-205
-
-
Dally, W.J.1
-
15
-
-
79953230724
-
-
presented at the Applied Power Electronics Conf.,Palm Springs, CA
-
G. Schrom, F. Faillet, and J. Hahn, "A 60 MHz 50Wfine-grain package integrated VR powering a CPU from 3.3 V," presented at the Applied Power Electronics Conf., Palm Springs, CA, 2010.
-
(2010)
A 60 MHz 50Wfine-Grain Package Integrated VR Powering a CPU from 3.3 V
-
-
Schrom, G.1
Faillet, F.2
Hahn, J.3
-
16
-
-
30344437884
-
Synchro-tokens: A deterministic GALS methodology for chip-level debug and test
-
DOI 10.1109/TC.2005.203
-
M. W. Heath, W. P. Burleson, and I. G. Harris, "Synchro-tokens: A deterministic GALS methodology for chip-level debug and test," IEE Trans. Computers, vol. 54, pp. 1532-1546, 2005. (Pubitemid 43065942)
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.12
, pp. 1532-1546
-
-
Heath, M.W.1
Burleson, W.P.2
Harris, I.G.3
-
18
-
-
0037216878
-
A VLSI crossbar switch with wrapped wave front arbitration
-
Jan.
-
J. G. Delgado-Frias and G. B. Ratanpal, "A VLSI crossbar switch with wrapped wave front arbitration," IEEE Trans. Circuits and Systems, vol. 50, no. 1, pp. 135-141, Jan. 2007.
-
(2007)
IEEE Trans. Circuits and Systems
, vol.50
, Issue.1
, pp. 135-141
-
-
Delgado-Frias, J.G.1
Ratanpal, G.B.2
-
19
-
-
33748622010
-
The design and implementation of a low-latency on-chip network
-
1594676, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
-
R. Mullins, A. West, and S. Moore, "The design and implementation of a low- latency on-chip network," in Proc. ASP-DAC, 2006, pp. 164-169. (Pubitemid 44375921)
-
(2006)
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
, vol.2006
, pp. 164-169
-
-
Mullins, R.1
West, A.2
Moore, S.3
-
20
-
-
46449125129
-
Design of a dynamic priority-based fast path architecture for on-chip interconnects
-
D. Park et al., "Design of a dynamic priority-based fast path architecture for on-chip interconnects," in IEEE Symp. High-Performance Interconnects, 2007, pp. 15-20.
-
(2007)
IEEE Symp. High-Performance Interconnects
, pp. 15-20
-
-
Park, D.1
|