Enabling improved power management in multicore processors through clustered DVFS

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 293-298

  Kolpe, Tejaswini ^a   Zhai, Antonia ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; CHIP MULTIPROCESSORS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; HIGH SPEED COMPUTING; MULTI-CORE PROCESSOR; ON-CHIP VOLTAGE REGULATOR; POWER DISSIPATION; POWER MANAGEMENTS; POWER REDUCTIONS;

ELECTRIC POTENTIAL; PROGRAM PROCESSORS; VOLTAGE REGULATORS;

ENERGY MANAGEMENT;

EID: 79957558684     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Y. Li, K. Skadron, D. Brooks, and Z. Hu. Performance, energy, and thermal considerations for SMT and CMP architectures. In Proceedings of the International Symposium on High-Performance Computer Architecture, pages 71-82, 2005.
2. L. Hammond, B. A. Nayfeh, and K. Olukotun. A single-chip multiprocessor. IEEE Computer, 30(9):79-85, 1997. (Pubitemid 127672649)
3. W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the International Symposium on High-Performance Computer Architecture, pages 123-134, 2008.
4. S. Herbert and D. Marculescu. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 38-43, 2007.
5. P. Juang, Q.Wu, L.-S. Peh, M. Martonosi, and D.W. Clark. Coordinated, distributed, formal energy management of chip multiprocessors. In Proceedings of the International Symposium on Low Power Electronics and Design, 2005.
6. J. Li and J. F. Martínez. Dynamic power-performance adaptation of parallel computation on chip multiprocessors. In Proceedings of the International Symposium on High-Performance Computer Architecture, 2006.
7. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, and Margaret Martonosi. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the International Symposium on Microarchitecture, pages 347-358, December 2006.
8. M. Martonosi and S. Kaxiras. Computer Architecture Techniques for Power-Efficiency. Morgan and Claypool, San Rafael, CA, first edition, 2008.
9. D. Burger and T. M. Austin. The SimpleScalar tool set, Version 2.0. ACM SIGARCH Computer Architecture News, 25:13-25, 1997.
10. A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of Design, Automation & Test in Europe, pages 423-428, 2009.
11. AJ KleinOsowski and D. J. Lilja. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters, 1:7-7, 2002.
12. J. Howard et al., A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. In Digest of Technical Papers, International Solid-State Circuits Conference, pages 108-109, 2010.