Impact of strained-Si PMOS transistors on SRAM soft error rates

IEEE Transactions on Nuclear Science

Volumn 59, Issue 4 PART 1, 2012, Pages 845-850

  Mahatme, Nihaar N ^a   Bhuva, Bharat L ^a   Fang, Yi Pin ^b   Oates, Anthony S ^b  

^a VANDERBILT UNIVERSITY   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Deep N Well; Si Ge PMOS; single event upsets; SRAMs

Indexed keywords

BULK CMOS; DEEP SUB-MICRON TECHNOLOGY; DEEP-N-WELL; MULTIPLE-CELL UPSETS; PMOS TRANSISTORS; SI-GE PMOS; SINGLE EVENT UPSETS; SOFT ERROR RATE; SRAMS; STRAINED-SI;

GERMANIUM;

SILICON;

EID: 84865383032     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2012.2188040     Document Type: Article

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