A highly scaled, high performance 45nm bulk logic CMOS technology with 0.242 μm2 SRAM cell

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 243-246

  Cheng, Kuan Lun ^a   Wu, C C ^a   Wang, Y P ^a   Lin, D W ^a   Chu, C M ^a   Tamg, Y Y ^a   Lu, S Y ^a   Yang, S J ^a   Hsieh, M H ^a   Liu, C M ^a   Fu, S P ^a   Chen, J H ^a   Lin, C T ^a   Lien, W Y ^a   Huang, H Y ^a   Wang, P W ^a   Lin, H H ^a   Lee, D Y ^a   Huang, M J ^a   Nieh, C F ^a   Lin, L T ^a   Chen, C C ^a   Chang, W ^a   Chiu, Y H ^a   Wang, M Y ^a   Yeh, C H ^a   Chen, F C ^a   Wu, C M ^a   Chang, Y H ^a   Wang, S C ^a   Hsieh, H C ^a   Lei, M D ^a   Goto, K ^a   Tao, H J ^a   Cao, M ^a   Tuan, H C ^a   Diaz, C H ^a   Mii, Y J ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; LITHOGRAPHY;

45 NM TECHNOLOGY; BULK CMOS; CMOS TECHNOLOGIES; GATE DENSITY; IMMERSION LITHOGRAPHY; SCALING FACTORS;

TECHNOLOGY;

EID: 50249177115     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418913     Document Type: Conference Paper

References (6)

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5. A. Eiho et al., VLSI Tech. Symp., p. 218, 2007
6. Y. Kumagai et al., Ext. Abstract SSDM, p. 14, 2002