A 0.5-V, 440-μW frequency synthesizer for implantable medical devices

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 8, 2012, Pages 1896-1907

  Chen, Wu Hsin ^a   Loke, Wing Fai ^a   Jung, Byunghoo ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

low power; low power electronics; low voltage; MedRadio; PLL; Wireless implantable devices

Indexed keywords

CHARGE PUMP; CMOS TECHNOLOGY; DESIGN TECHNIQUE; DRIVING CURRENT; FREQUENCY OFFSETS; IMPLANTABLE MEDICAL DEVICES; LOW POWER; LOW VOLTAGES; LOW-VOLTAGE; MEDRADIO; ULTRA-LOW POWER; ULTRALOW VOLTAGE; WIRELESS IMPLANTABLE DEVICES;

CIRCUIT OSCILLATIONS; CMOS INTEGRATED CIRCUITS; FREQUENCY ALLOCATION; FREQUENCY SYNTHESIZERS; IMPLANTS (SURGICAL); LOW POWER ELECTRONICS; PHASE LOCKED LOOPS;

BIOMEDICAL EQUIPMENT;

EID: 84864756884     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2196315     Document Type: Article

References (41)

1. K. D. Wise et al. , "Microelectrodes, microelectronics, and implantable neural microsystems," Proc. IEEE, vol. 96, no. 7, pp. 1184-1202, Jul. 2008.
2. Federal Commun. Comm. Std. Part 95-Personal Radio Services, , Mar. 2009.
3. D. Panescu, "Emerging technologies: Wireless communication systems for implantable medical devices," IEEE Eng. Med. Biol. Mag. , vol. 27, no. 2, pp. 96-101, Mar.-Apr. 2008. (Pubitemid 351374193)
4. J. L. Bohorquez, A. P. Chandrakasan, and J. L. Dawson, "A 350 W CMOS MSK transmitter and 400 W OOK super-regenerative receiver for medical implant communications," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1248-1259, Apr. 2009.
5. P. Cong et al. , "A wireless and batteryless 10-bit implantable blood pressure sensing microsystem with adaptive RF powering for real-time laboratory mice monitoring," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3631-3644, Dec. 2009.
6. P. D. Bradley, "An ultra low power, high performance medical implant communication system (MICS) transceiver for implantable devices," in Proc. IEEE Biomedical Circuits and Syst. Conf. (BioCAS), Dec. 2006, pp. 158-161.
7. H.-H. Hsieh, C.-T. Lu, and L.-H. Lu, "A 0. 5-V 1. 9-GHz low-power phase-locked loop in 0. 18-m CMOS," in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2007, pp. 164-165. (Pubitemid 351306607)
8. T.-S. Chao et al. , "Designing ultra-lowvoltage PLL using a bulk-driven technique," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2009, pp. 388-391.
9. S.-A. Yu and P. Kinget, "A 0. 65-V 2. 5-GHz fractional-N synthesizer with two-point 2-Mb/s GFSK data modulation," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2411-2425, Sep. 2009.
10. A. Balankutty et al. , "A 0. 6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2. 4-GHz ISM-band applications," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 538-553, Mar. 2010.
11. J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, "A 0. 5-V 1-W successive approximation ADC," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, Jul. 2003.
12. N. Stanic, P. Kinget, and Y. Tsividis, "A 0. 5 V 900 MHz CMOS receiver front end," in Proc. Symp. VLSI Circuits (VLSIC), 2006, pp. 228-229. (Pubitemid 351306354)
13. I. Akita, K. Wada, and Y. Tadokoro, "A 0. 6-V dynamic biasing filter with 89-dB dynamic range in 0. 18-m CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2790-2799, Oct. 2009.
14. K.-H. Cheng et al. , "A 0. 5-V 0. 4-2. 24-GHz inductorless phase-locked loop in a system-on-chip," IEEE Trans. Circuits Syst. I, vol. 58, no. 5, pp. 849-859, May 2011.
15. W.-H. Chen et al. , "A 0. 5-V, 440-W frequency synthesizer for implantable medical devices," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2011, pp. 1-4.
16. W.-F. Loke et al. , "A 0. 5-V sub-mW wireless magnetic tracking transponder for radiation therapy," in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2011, pp. 172-173.
17. S. Bazarjani and W. Snelgrove, "Low voltage SC circuit design with low-Vt MOSFETs," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Apr. 1995, vol. 2, pp. 1021-1024.
18. T. Ohguro et al. , "0. 18 m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique," in Proc. Int. Electron Devices Meeting (IEDM), Dec. 1997, pp. 837-840.
19. A. Jimenez-P, F. de la Hidalga-W, and M. Deen, "Modelling of the dynamic thresholdMOSFET," in IEE Proc.-Circuits, Devices and Syst. , Oct. 2005, vol. 152, no. 5, pp. 502-508.
20. J. Zhou and Z. Wang, "A high-performance CMOS charge-pump for phase-locked loops," in Proc. Int. Conf. Microwave and Millimeter Wave Technology, Apr. 2008, vol. 2, pp. 839-842.
21. B. Sheu and P. Ko, "Measurement andmodeling of short-channelMOS transistor gate capacitances," IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp. 464-472, Jun. 1987.
22. H. Iwai et al. , "Analysis of velocity saturation and other effects on short-channel MOS transistor capacitances," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol. 6, no. 2, pp. 173-184, Mar. 1987. (Pubitemid 17548911)
23. R. Sarpeshkar, Ultra Low Power Bioelectronics: Fundamentals, Biomedical Applications, and Bio-Inspired Systems. NewYork,NY: Cambridge University Press, 2010.
24. H.-H. Hsieh and L.-H. Lu, "A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations," IEEE Trans. Microw. Theory Tech. , vol. 55, no. 3, pp. 467-473, Mar. 2007. (Pubitemid 46393310)
25. S.-L. Jang et al. , "A 0. 3 V cross-coupled VCO using dynamic threshold MOSFET," IEEE Microw. Wireless Compon. Lett. , vol. 20, no. 3, pp. 166-168, Mar. 2010.
26. A. Abidi, "Phase noise and jitter in CMOS ring oscillators," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006. (Pubitemid 44192106)
27. D. Ham and A. Hajimiri, "Concepts and methods in optimization of integrated LC VCOs," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909, Jun. 2001. (Pubitemid 32576346)
28. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operations," IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224-231, Jun. 1977.
29. C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design. Chicester, U. K. : Wiley, 2006.
30. P. E. Allen andD. R. Holberg, CMOS Analog CircuitDesign, 2nd ed. New York, NY: Oxford University Press, 2002.
31. B. Razavi, Design of Analog CMOS Integrated Circuits. NewYork, NY: McGraw-Hill, 2001.
32. W. Wilson et al. , "A CMOS self-calibrating frequency synthesizer," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
33. J.-S. Lee et al. , "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Lett. , vol. 36, no. 23, pp. 1907-1908, Nov. 2000. (Pubitemid 32022862)
34. J. N. Soares, Jr. and W. A. M. Van Noije, "A 1. 6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 97-102, Jan. 1999.
35. X. P. Yu et al. , "Design and optimization of the extended true singlephase clock-based prescaler," IEEE Trans. Microw. Theory Tech. , vol. 54, no. 11, pp. 3828-3835, Nov. 2006.
36. A. Wagemans et al. , "A 3. 5 mW2. 5 GHz diversity receiver and a 1. 2 mW 3. 6 GHz VCO in silicon-on-anything," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1998, pp. 250-251, 444.
37. A. Fahim, "A compact, low-power low-jitter digital PLL," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2003, pp. 101-104.
38. X. Gao et al. , "Jitter analysis and a benchmarking figure-of-merit for phase-locked loops," IEEE Trans. Circuits Syst. II, vol. 56, no. 2, pp. 117-121, Feb. 2009.
39. J. Kim et al. , "A 44 GHz differentially tuned VCO with 4 GHz tuning range in 0. 12 m SOI CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 416-607.
40. P. Raha, "A 0. 6-4. 2 V low-power configurable PLL architecture for 6 GHz-300MHz applications in a 90 nmCMOS process," in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2004, pp. 232-235.
41. C.-T. Lu, H.-H. Hsieh, and L.-H. Lu, "A low-power quadrature VCO and its application to a 0. 6-V 2. 4-GHz PLL," IEEE Trans. Circuits Syst. I, vol. 57, no. 4, pp. 793-802, Apr. 2010.