A high-performance CMOS charge-pump for phase-locked loops

2008 International Conference on Microwave and Millimeter Wave Technology Proceedings, ICMMT

Volumn 2, Issue , 2008, Pages 839-842

  Zhou, Jianzheng ^a,b   Wang, Zhigong ^a  

^a SOUTHEAST UNIVERSITY   (China)

^b HEFEI UNIVERSITY OF TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ERRORS; MICROWAVES; MILLIMETER WAVE DEVICES; MILLIMETER WAVES; NETWORKS (CIRCUITS); PUMPS;

INTERNATIONAL CONFERENCES; MILLIMETER-WAVE TECHNOLOGIES; NON-IDEAL EFFECTS;

SWITCHES;

EID: 51149091490     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMMT.2008.4540531     Document Type: Conference Paper

References (10)

1. Woogeun Rhee, "Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops," 1999 IEEE International Symposium on Circuits and Systems, ISCAS'99. Vol.2, pp. 545-548, 30 May-2 June 1999.
2. M.El-Hage and Fei Yuan, "Architectures and design considerations of CMOS charge pumps for phase-locked loops," IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2003, Vol.1, pp. 223-226, May 2003.
3. I.A. Young, J.K.Greason, and K.L.Wong, "A PLL clock generator with 5 to 10 MHz of lock range for microprocessors," IEEE Journal of Solid-State Circuits, Vol.27, No.11, pp. 1599-1607, Nov. 1992.
4. Y.-S.Choi and D.-H. Han, "Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop," IEEE Tran. on Circuits and Systems II: Express Briefs, Vol.53, No.10, pp. 1022-1025, Oct. 2006.
5. Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, and Suki Kim, "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Letters, Vol.36, No.23, pp. 1907-1908, Nov. 2000.
6. R.C. Chang and Lung-Chih Kuo, "A New Low-voltage Charge Pump Circuit for PLL," Proceedings the 2000 IEEE International Symposium on Circuits and Systems. ISCAS 2000 Geneva, Vol.5, pp. 701-704, May 2000.
7. E. J. Hernandez and A. D. Sanchez, "A novel CMOS charge-pump circuit with positive feedback for PLL applications," The 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001. Vol.1, pp. 349-352, Sept. 2001.
8. Hong Yu, Yasuaki Inoue, and Yan Han, "A new high-speed low-voltage charge pump for PLL applications," 6th International Conference On ASIC, ASICON 2005, Vol.1, pp. 387-390, Oct. 2005.
9. L. Dai and R. Harjani, "CMOS Switched-Op-Amp-Based Sample-and-Hold Circuit," IEEE J. Solid-State Circuits, Vol. 35, No.1, pp.109-113, January 2000.
10. Chih-Ming Hung and K.O. Kenneth, "A Fully 1.5V 5.5CHz CMOS Phase-Locked Loop," IEEE Journal of Solid-State Circuits, Vol.37, No.4, pp. 521-525, April 2002.