Modelling of the dynamic threshold MOSFET

IEE Proceedings: Circuits, Devices and Systems

Volumn 152, Issue 5, 2005, Pages 502-508

  Jimenez P A ^a   De La Hidalga, F J W ^a   Deen, M J ^b  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FIELDS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; POISSON EQUATION; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

DEPLETION REGION; DYNAMIC THRESHOLD VOLTAGE MOSFETS (DTMOS); SUBMICRON TECHNOLOGIES; SUBSTRATE DOPING;

MOSFET DEVICES;

EID: 27544448587     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20045047     Document Type: Conference Paper

References (14)

1. Assaderaghi, F., Sinitsky, D., Parke, S., Bokor, J., Ko, P.K., and Hu, C.: 'A dynamic threshold voltage MOSFET (DTMOS) for ultralow-voltage operation'. IEEE IEDM, 1994
2. Kotaki, H., Kakimoto. S., Nakano, M., Matsuoka, T., Adachi, K., Sugimoto, K., Fukushima, T., and Sato, Y.: 'Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS'. IEEE IEDM, 1996
3. Kotaki, H., Kakimoto, S., Nakano, M., Adachi, K., Shibata, A., Sugimoto, K., Ohta, K., and Hashizume, N.: 'Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology'. IEEE IEDM, 1998
4. Takamiya, M., and Hiramoto, T.: 'High drive-current electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltage', IEEE Trans. Electron Devices, 2001, 48, pp. 1633-1640
5. Chang, S.J., Chang, C.Y., Chen, C., Chao, T.S., Lee, Y.J., and Huang, T.Y.: 'High performance and high-reliability 80-nm gatelength DTMOS with indium super steep retrograde channel', IEEE Trans. Electron Devices, 2000, 47, pp. 2379-2384
6. Takagi, T., Inoue, A., Hara. Y., Kanzawa, Y., and Kubo, M.: 'A novel high performance SiGe channel heterostructure dynamic threshold p-MOSFET (HDTMOS)'. IEEE Electron Device Lett., 2001, 22, pp. 206-208
7. Chung, I.Y., Park, Y.J., and Min, H.S.: 'A new SOI inverter using dynamic threshold for low-power applications'. IEEE Electron Device Lett., 1997, 18, pp. 248-250
8. Casu, M.R., Masera, G., Piccinini, G., Roch, M.R., and Zamboni, M.: 'Comparative analysis of PD-SOI active body-biasing circuits'. Proc. IEEE Int. SOI Conf., 2000, pp. 94-95
9. Yan, Z., Deen, M.J., and Malhi, D.S.: 'Gate-controlled lateral PNP BJT: characteristics, modelling and circuit applications', IEEE Trans. Electron Devices, 1997, 44, pp. 118-128
10. Assaderaghi, F., Sinitsky, D., Parke, S., Bokor, J., Ko, P.K., and Hu, C.: 'Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI', IEEE Trans. Electron Devices, 1997, 44, pp. 414-422
11. McKinnon, W.R., Ferguson, R., and McAlister, S.P.: 'A model for gate-lateral BJTs based on standard MOSFET models', IEEE Trans. Electron Devices, 1999, 46, pp. 427-429
12. Yamamoto, T., Mogami, T., and Terada, K.: 'A new CMOS structure for low temperature operation with forward substrate bias'. IEEE Symp. on VLSI Technology Digest of Technical Papers, 1992, pp. 104
13. Mohammadi, S., and Selvakumar, C.R.: 'Calculation of depletion layer thickness by including the mobile carriers', IEEE Trans. Electron Devices, 1996, 43, (1), pp. 185-188
14. De la Hidalga-W, F.J., Deen. M.J., Gutiérrez, E.A., and Balestra, F.: 'Effect of the forward biasing the source-substrate junction in n-MOS transistors for possible low power CMOS integrated circuits applications', J. Vac. Sci. Technol., 1998, B16, (4), pp. 1812-1817