Design and optimization of the extended true single-phase clock-based prescaler

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 11, 2006, Pages 3828-3834

  Yu, Xiao Peng ^a,b   Do, Manh Anh ^a,c   Lim, Wei Meng ^c   Yeo, Kiat Seng ^c   Ma, Jian Guo ^a,d  

^a IEEE   (Singapore)

^b ZHEJIANG UNIVERSITY   (China)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

Author keywords

CMOS integrated circuit; D flip flop (DFF); Frequency divider; Frequency synthesizer; High speed digital circuit; Phase locked loops (PLLs); True single phase clock (TSPC)

Indexed keywords

D FLIP-FLOP (DFF); HIGH-SPEED DIGITAL CIRCUITS; TRUE SINGLE-PHASE CLOCK (TSPC);

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; FREQUENCY SYNTHESIZERS; LOCAL AREA NETWORKS; OPTIMIZATION; PRODUCT DEVELOPMENT; SHORT CIRCUIT CURRENTS;

FREQUENCY DIVIDING CIRCUITS;

EID: 33750808146     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2006.884629     Document Type: Article

References (9)

1. S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, "A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb. 2004.
2. J. N. Soares, Jr. and W. A. M. Van Noije, "A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 97-102, Jan. 1999.
3. R. X. Gu, K. M. Sharaf, and M. I. Elmasry, High-Performance Digital VLSI Circuit Design. Norwell, MA: Kluwer, 1996.
4. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, A Design Perspective, ser. Electron, and VLSI, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003.
5. A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
6. R. Rogenmoser, The Design of High-Speed Dynamic CMOS Circuits for VLSI, ser. Microelectron., 1. Aufl ed. Konstanz, Germany: Hartung-Gorre, 1996.
7. C. Lam and B. Razavi, "A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 788-794, May 2000.
8. Q. Huang and R. Rogenmoser, "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 456-465, Mar. 1996.
9. X. P. Yu, M. A. Do, L. Jia, J. G. Ma, and K. S. Yeo, "Design of a low power wideband high resolution programmable frequency divider," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 9, pp. 1098-1103, Sep. 2005.