Cascading wafer-scale integrated graphene complementary inverters under ambient conditions

Nano Letters

Volumn 12, Issue 8, 2012, Pages 3948-3953

  Rizzi, Laura Giorgia ^a   Bianchi, Massimiliano ^a   Behnam, Ashkan ^b   Carrion, Enrique ^b   Guerriero, Erica ^a   Polloni, Laura ^a,c   Pop, Eric ^b,d   Sordan, Roman ^a  

^a POLITECNICO DI MILANO   (Italy)

^b University of Illinois at Urbana Champaign   (United States)

^c UNIVERSITY OF INSUBRIA   (Italy)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

digital electronics; Graphene; integrated circuit; logic gates; voltage gain

Indexed keywords

AIR AMBIENT; AMBIENT CONDITIONS; COMPLEMENTARY INVERTERS; DIGITAL ELECTRONICS; EMITTER COUPLED LOGIC; FUNDAMENTAL BUILDING BLOCKS; GRAPHENE DEVICES; HIGH-SPEED OPERATION; INPUT AND OUTPUTS; LOGIC FUNCTIONS; LOGIC LEVELS; LOW FREQUENCY; REALISTIC APPLICATIONS; SELF-ALIGNED; SIGNAL MATCHING; SOURCE AND DRAINS; TOP GATE; VOLTAGE GAIN; VOLTAGE SWINGS; WAFER-SCALE;

CHEMICAL VAPOR DEPOSITION; DIGITAL INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; GAIN MEASUREMENT; INTEGRATED CIRCUITS; LOGIC GATES; MONOLAYERS;

GRAPHENE;

EID: 84864652610     PISSN: 15306984     EISSN: 15306992     Source Type: Journal    
DOI: 10.1021/nl301079r     Document Type: Article

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