Carry chains for ultra high-speed SiGe HBT adders

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 9, 2011, Pages 2201-2210

  Gutin, Alexey ^a   Jacob, Philip ^b   Chu, Michael ^a   Belemjian, Paul M ^c   Leroy, Mitchell R ^a   Kraft, Russell P ^a   McDonald, John F ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c NAVAL RESEARCH LABORATORY   (United States)

Author keywords

Adders; bipolar integrated circuits; carry look ahead; CML; ECL; HBT; SiGe

Indexed keywords

ADDERS; BIPOLAR INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMITTER COUPLED LOGIC CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; PRODUCT DESIGN; SILICON;

CARRY LOOK-AHEAD; DEVICE TEMPERATURE; DIGITAL APPLICATIONS; INTEGER ARITHMETIC; LOW-POWER DESIGN; POWER DELAY PRODUCT; SIGE; ULTRA HIGH SPEED;

SI-GE ALLOYS;

EID: 80052904744     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2112850     Document Type: Article

References (34)

1. K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young, "Interconnects in the third dimension: Design challenges for 3D ICs," in Proc. 44th Design Autom. Conf., 2007, pp. 562-567. (Pubitemid 47130028)
2. G. M. Amdahl, "Validity of the single processor approach to achieving large scale computing capabilities," in Proc. AFIPS Conf., 1967, pp. 483-485.
3. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, "An 8.3 GHz dual supply/threshold optimized 32 b integer ALU-register file loop in 90 nm CMOS," in Proc. ISLPED'05, Aug. 2005, pp. 103-106. (Pubitemid 41731635)
4. S. R. Carlough et al., "A 2 GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 885-894, Jun. 2000.
5. C. G. Ekroot and S. I. Long, "A GaAs 4-bit adder-accumulator circuit for direct digital synthesis," IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 573-580, Apr. 1988.
6. S. E. Turner, R. B. Elder, D. S. Jansen, and D. E. Kotecki, "4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology," IEEE Microw. Wireless Compon. Lett., vol. 15, no. 3, pp. 144-146, Mar. 2005. (Pubitemid 40421596)
7. T. Mathew et al., "2-bit adder: Carry and sum logic circuits at 19 GHz clock frequency in InAlAs/InGaAs HBT technology," Electron. Lett., vol. 37, no. 19, pp. 1156-1157, Sep. 2001. (Pubitemid 32909364)
8. A. Bellaouar and H. Touzene, "3.3 V BiCMOS current mode logic circuits for high speed adders," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1165-1169, Aug. 1996. (Pubitemid 126580910)
9. L. J. Micheel, "Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers," in Proc. 22nd Int. Symp. Multiple-Valued Logic, May 1992, pp. 18-26.
10. H. Greub, J. F. McDonald, T. Creedon, and T. Yamaguchi, "High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic," IEEE J. Solid-State Circuits, vol. 26, no. 5, pp. 749-762, May 1991. (Pubitemid 21646265)
11. M. Alioto and G. Palumbo, "CML and ECL: Optimized design and comparison," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 11, pp. 1330-1341, Nov. 1999. (Pubitemid 30519689)
12. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, "An 8.3 GHz dual supply/threshold optimized 32 b integer ALU-register file loop in 90 nm CMOS," in Proc. ISLPED'05, Aug. 2005, pp. 105-106.
13. H. Ling, "High-speed binary adder," IBM J. Research Develop., vol. 25, no. 3, pp. 156-166, May 1981.
14. T. Han and D. A. Carlson, "Fast area-efficient VLSI adders," in Proc. 8th Symp. Comput. Arith., May 1987, pp. 49-56.
15. T. Kilburn, D. B. G. Edwards, and D. Aspinall, "Parallel addition in digital computers: A new fast "carry" circuit," Proc. IEE, vol. 106, pt. B, p. 464, Sep. 1959.
16. O. J. Bedrij, "Carry-select adder," IRE Trans. Electron. Comput., vol. EC-11, no. 3, pp. 340-346, Jun. 1962.
17. V. G. Oklobdija and E. R. Barnes, "Some optimal schemes for ALU implementation in VLSI technology," in Proc. 7th IEEESymp. Comput. Arith., 1985, pp. 2-8.
18. R. P. Brent and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, no. 3, pp. 260-264, Mar. 1982.
19. G. Bewick, P. Song, G. De Micheli, and M. Flynn, "Approaching a nanosecond: A 32 bit adder," in Proc. Int. Conf. Circuit Comput. Design, 1988, pp. 221-226.
20. P. F. Stelling and V. G. Oklobdzija, "Design strategies for optimal hybrid final adders in a parallel multiplier," J. VLSI Signal Process., vol. 14, pp. 321-331, Dec. 1996.
21. A. J. Joseph, D. L. Harame, B. Jagannathan, D. Coolbaugh, D. Ahlgren, and J. Magerlein et al., "Status and direction of communication technologies-SiGeBiCMOS and RFCMOS," Proc. IEEE, vol. 93, no. 9, pp. 1539-1558, Sep. 2005.
22. D. L. Harame and B. S. Meyerson, "The early history of IBM's SiGe mixed signal technology," IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2555-2567, Nov. 2001. (Pubitemid 33105914)
23. E. Crabbe, B. Meyerson, D. Harame, J. Stork, A. Megdanis, J. Cotte, J. Chu, M. Gilbert, C. Stanis, J. Comfort, G. Patton, and S. Subbanna, "113-GHzft graded-base SiGe HBT's," IEEE Trans. Electron Devices, vol. 40, no. 11, pp. 2100-2101, Nov. 1993.
24. T. O. Dickson, K. H. K. Yau, T. Chalvatzis, A. M. Mangan, E. Laskin, R. Beerkens, P. Westergaard, M. Tazlauanu, M.-T. Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1830-1845, Aug. 2006.
25. , J. Cressler, Ed., Silicon Heterostructure Handbook. Boca Raton, FL: CRC, 2006.
26. P. Solomon and D. Tangc, "Bipolar circuit scaling," in ISSCC Dig. Tech. Papers, 1979, pp. 86-87.
27. S. A. Steidl and J. F. McDonald, "A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 228-236, Feb. 2002. (Pubitemid 34278438)
28. M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic. New York: Springer, 2005.
29. T. Han and D. A. Carlson, "Fast area-efficient VLSI adders," in Proc. 8th Symp. Comput. Arith., May 1987, pp. 49-56.
30. H. Ling, "High-speed binary parallel adder," Trans. Electron. Comput., vol. EC-15, no. 10, pp. 799-802, Oct. 1966.
31. M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design. New York: Wiley, 2001.
32. P. Belemjian, O. Erdogan, R. Kraft, and J. F. McDonald, "SiGe HBT microprocessor core test vehicle," Proc. IEEE, vol. 93, no. 9, pp. 540-547, Sep. 2005.
33. K. Zhou and J. F. McDonald, "Impact of deep trench sharing isolation on ultra-high-speed digital systems," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 10, pp. 778-782, Oct. 2009.
34. S. Thuries, E. Tournier, and J. Graffeuil, "A 3-bits DDS oriented low power consumption 15 GHz phase accumulator in a 0.25 lim BiC-MOSSiGe:C technology," in IEEE Int. Conf. Electron., Circuits Syst., Dec. 10-13, 2006, pp. 991-994.