메뉴 건너뛰기




Volumn 19, Issue 1-3, 2012, Pages 185-201

Reducing reversible circuit cost by adding lines

Author keywords

Optimization; Quantum circuits; Reversible logic

Indexed keywords

AUTOMATED SYNTHESIS; CIRCUIT OPTIMIZATION; LOW-POWER DESIGN; QUANTUM CIRCUIT; QUANTUM COSTS; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC;

EID: 84864054460     PISSN: 15423980     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (26)
  • 3
    • 0015680909 scopus 로고
    • Logical reversibility of computation
    • C. H. Bennett. (1973). Logical reversibility of computation. IBM J. Res. Dev, 17(6):525-532.
    • (1973) IBM J. Res. Dev , vol.17 , Issue.6 , pp. 525-532
    • Bennett, C.H.1
  • 4
    • 0036900183 scopus 로고    scopus 로고
    • A reversible carry-look-ahead adder using control gates
    • DOI 10.1016/S0167-9260(02)00051-2, PII S0167926002000512
    • B. Desoete and A. deVos. (2002). A reversible carry-look-ahead adder using control gates. INTEGRATION, the VLSI Journal, 33(1-2):89-104. (Pubitemid 35459786)
    • (2002) Integration, the VLSI Journal , vol.33 , Issue.1-2 , pp. 89-104
    • Desoete, B.1    De Vos, A.2
  • 5
    • 42149155654 scopus 로고    scopus 로고
    • Reversible logic synthesis with Fredkin and peres gates
    • J. Donald and N. K. Jha. (2008). Reversible logic synthesis with Fredkin and Peres gates. J. Emergin Technology Computing Systems, 4(1):1-19.
    • (2008) J. Emergin Technology Computing Systems , vol.4 , Issue.1 , pp. 1-19
    • Donald, J.1    Jha, N.K.2
  • 7
    • 33750588847 scopus 로고    scopus 로고
    • An algorithm for synthesis of reversible logic circuits
    • Nov
    • P. Gupta, A. Agrawal, , and N. K Jha. (Nov. 2006). An algorithm for synthesis of reversible logic circuits. IEEE Trans. on CAD, 25(11):2317-2330.
    • (2006) IEEE Trans. on CAD , vol.25 , Issue.11 , pp. 2317-2330
    • Gupta, P.1    Agrawal, A.2    Jha, N.K.3
  • 8
  • 9
    • 0000328287 scopus 로고
    • Irreversibility and heat generation in the computing process
    • R. Landauer. (1961). Irreversibility and heat generation in the computing process. IBM J. Res. Dev., 5:183.
    • (1961) IBM J. Res. Dev. , vol.5 , pp. 183
    • Landauer, R.1
  • 10
    • 8344281996 scopus 로고    scopus 로고
    • Reversible cascades with minimal garbage
    • D. Maslov and G. W. Dueck. (2004). Reversible cascades with minimal garbage. IEEE Trans. on CAD, 23(11):1497-1509.
    • (2004) IEEE Trans. on CAD , vol.23 , Issue.11 , pp. 1497-1509
    • Maslov, D.1    Dueck, G.W.2
  • 11
  • 13
    • 0043136670 scopus 로고    scopus 로고
    • A transformation based algorithm for reversible logic synthesis
    • D. M. Miller, D. Maslov, and G.W. Dueck. (2003). A transformation based algorithm for reversible logic synthesis. In Proc. Design Automation Conf., pages 318-323.
    • (2003) Proc. Design Automation Conf. , pp. 318-323
    • Miller, D.M.1    Maslov, D.2    Dueck, G.W.3
  • 15
  • 16
    • 36348950128 scopus 로고    scopus 로고
    • On the behavior of substitution-based reversible circuit synthesis algorithms: Investigation and improvement
    • M. Saeedi, M. S. Zamani, and M. Sedighi. (2007). On the behavior of substitution-based reversible circuit synthesis algorithms: Investigation and improvement. In Proc. IEEE Computer Society Symp. on VLSI, pages 428-436.
    • (2007) Proc. IEEE Computer Society Symp. on VLSI , pp. 428-436
    • Saeedi, M.1    Zamani, M.S.2    Sedighi, M.3
  • 20
    • 47349093138 scopus 로고    scopus 로고
    • Optimized reversible binary-coded decimal adders
    • M. K. Thomson and R. Glück. (2008). Optimized reversible binary-coded decimal adders. J. of Systems Architecture, 54:697-706.
    • (2008) J. of Systems Architecture , vol.54 , pp. 697-706
    • Thomson, M.K.1    Glück, R.2
  • 21
    • 70350712413 scopus 로고    scopus 로고
    • BDD-based synthesis of reversible logic for large functions
    • R. Wille and R. Drechsler. (2009). BDD-based Synthesis of Reversible Logic for Large Functions. In Proc. Design Automation Conf., pages 270-275.
    • (2009) Proc. Design Automation Conf. , pp. 270-275
    • Wille, R.1    Drechsler, R.2
  • 22
    • 62949164659 scopus 로고    scopus 로고
    • Reversible logic synthesis with output permutation
    • R. Wille, D. Große, G.W. Dueck, and R. Drechsler. (2009). Reversible Logic Synthesis with Output Permutation. In VLSI Design, pages 189-194.
    • (2009) VLSI Design , pp. 189-194
    • Wille, R.1    Große, D.2    Dueck, G.W.3    Drechsler, R.4
  • 24
    • 50449097451 scopus 로고    scopus 로고
    • Revlib: An online resource for reversible functions and reversible circuits
    • RevLib is
    • R.Wille, D. Große, L. Teuber, G.W. Dueck, and R. Drechsler. (2008). RevLib: An online resource for reversible functions and reversible circuits. In Int'l Symp. on Multi-Valued Logic, pages 220-225. RevLib is available at www.revlib.org.
    • (2008) Int'l Symp. on Multi-Valued Logic , pp. 220-225
    • Wille, R.1    Große, D.2    Teuber, L.3    Dueck, G.W.4    Drechsler, R.5
  • 25
    • 3142722173 scopus 로고    scopus 로고
    • Limits to binary logic switch scaling - A gedanken model
    • DOI 10.1109/JPROC.2003.818324, Nanoelectronics and Nanoscale Precessing
    • V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff. (2003). Limits to binary logic switch scaling - a gedanken model. Proc. of the IEEE, 91(11):1934-1939. (Pubitemid 40890796)
    • (2003) Proceedings of the IEEE , vol.91 , Issue.11 , pp. 1934-1939
    • Zhirnov, V.V.1    Cavin III, R.K.2    Hutchby, J.A.3    Bourianoff, G.I.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.