Limits to binary logic switch scaling - A gedanken model

Proceedings of the IEEE

Volumn 91, Issue 11, 2003, Pages 1934-1939

  Zhirnov, Victor V ^a,b   Cavin III, Ralph K ^a   Hutchby, James A ^a   Bourianoff, George I ^a,c  

^a SEMICONDUCTOR RESEARCH CORPORATION   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Closely packed devices; Device scaling limits; Digital integrated circuits; Heat removal; Nanotechnology; Power consumption; Tunneling

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRON TUNNELING; ENERGY DISSIPATION; ENERGY UTILIZATION; NANOTECHNOLOGY; POWER ELECTRONICS; SWITCHING CIRCUITS; VLSI CIRCUITS;

CLOSELY PACKED DEVICES; DEVICE SCALING LIMITS; HEAT REMOVAL; POWER CONSUMPTION; TUNNELING;

LOGIC DEVICES;

EID: 3142722173     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.818324     Document Type: Conference Paper

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