Equivalence checking of reversible circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2009, Pages 324-330

  Wille, Robert ^a   Grobe, Daniel ^a   Miller, Michael D ^b   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b UNIVERSITY OF VICTORIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN SATISFIABILITY; COMMON SPECIFICATION; DECISION DIAGRAM; EQUIVALENCE CHECKING; GARBAGE OUTPUT; LOGIC STATE; MEMORY REQUIREMENTS; PRIMARY INPUTS; QUANTUM GATES; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC GATES; TARGET FUNCTIONS;

BOOLEAN FUNCTIONS; LOGIC GATES; MANY VALUED LOGICS; QUANTUM ELECTRONICS; SPECIFICATIONS;

LOGIC CIRCUITS;

EID: 70349409362     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISMVL.2009.19     Document Type: Conference Paper

References (20)

1. D. Brand. Verification of large synthesized designs. In Int'l Conf. on CAD, pages 534-537, 1993.
2. S. Cook. The complexity of theorem proving procedures. In 3. ACM Symposium on Theory of Computing, pages 151- 158, 1971.
3. N. Éen and N. Sórensson. An extensible SAT solver. In SAT 2003, volume 2919 of LNCS, pages 502-518, 2004.
4. E. F. Fredkin and T. Toffoli. Conservative logic. International Journal of Theoretical Physics, 21(3/4):219-253, 1982.
5. D. GroΒe, R. Wille, G. W. Dueck, and R. Drechsler. Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares. In Int'l Symp. on Multi-Valued Logic, pages 214-219, 2008.
6. J. Marques-Silva and K. Sakallah. GRASP: A search algorithm for propositional satisfiability. IEEE Trans. on Comp., 48(5):506-521, 1999.
7. D. M. Miller. Decision diagram techniques for reversible and quantum circuits. In 8th International Boolean Problems Workshop, pages 1-15, 2008.
8. D. M. Miller and M. A. Thornton. QMDD: A decision diagram structure for reversible and quantum circuits. In Proc. Int'l Symp. on Multiple-valued Logic, 2006.
9. D. M. Miller and M. A. Thornton. Multiple-Valued Logic: Concepts and Representations. Morgan and Claypool, 2008.
10. J. Mohnke, P. Molitor, and S. Malik. Limits of using signatures for permutation independent Boolean comparison. In ASP Design Automation Conf., pages 459-464, 1995.
11. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001.
12. M. Nielsen and I. Chuang. Quantum Computation and Quantum Information. Cambridge Univ. Press, 2000.
13. A. Peres. Reversible logic and quantum computers. Phys. Rev. A, (32):3266-3276, 1985.
14. T. Toffoli. Reversible computing. InW. de Bakker and J. van Leeuwen, editors, Automata, Languages and Programming, page 632. Springer, 1980. Technical Memo MIT/LCS/TM- 151, MIT Lab. for Comput. Sci.
15. G. F. Viamontes, I. L. Markov, and J. P. Hayes. Checking equivalence of quantum circuits and states. In Int'l Conf. on CAD, pages 69-74, 2007.
16. S.-A. Wang, C.-Y. Lu, I.-M. Tsai, and S.-Y. Kuo. An xqdd-based verification method for quantum circuits. IEICE Transactions, 91-A(2):584-594, 2008.
17. R. Wille and D. GroΒe. Fast exact Toffoli network synthesis of reversible logic. In Int'l Conf. on CAD, pages 60-64, 2007.
18. R. Wille, D. GroΒe, S. Frehse, G. W. Dueck, and R. Drechsler. Debugging of toffoli networks. In Design, Automation and Test in Europe, 2009.
19. R. Wille, D. GroΒe, L. Teuber, G. W. Dueck, and R. Drechsler. RevLib: An online resource for reversible functions and reversible circuits. In Int'l Symp. on Multi- Valued Logic, pages 220-225. RevLib is available at http://www.revlib.org.
20. S. Yamashita, S. ichi Minato, and D. M. Miller. An efficient verification of quantum circuits under a practical restriction. In Proc IEEE Int'l Conf. on Computer and Information Technology, pages 873-879, 2008.