Optimized reversible binary-coded decimal adders

Journal of Systems Architecture

Volumn 54, Issue 7, 2008, Pages 697-706

  Thomsen, Michael Kirkedal ^a   Glück, Robert ^a  

^a UNIVERSITY OF COPENHAGEN   (Denmark)

Author keywords

Application of reversible logic synthesis; Binary coded decimal; Full adder; Half adder; Parallel adder; Reversible logic circuit

Indexed keywords

ADDERS; FUZZY LOGIC; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; SWITCHING CIRCUITS; SWITCHING THEORY;

BINARY CODED DECIMAL (BCD) ADDER; BINARY NUMBERS; CIRCUIT COMPONENTS; CIRCUIT DELAYS; CMOS GATES; ELSEVIER (CO); FULL ADDERS (FA); LOW POWERS; ORIGINAL DESIGN; REVERSIBLE LOGIC SYNTHESIS; REVERSIBLE LOGICS; SYNTHESIS ALGORITHMS; SYSTEMS ARCHITECTURES;

LOGIC CIRCUITS;

EID: 47349093138     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2007.12.006     Document Type: Article

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