A hash-based approach for functional regularity extraction during logic synthesis

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 92-97

  Rosiello, Angelo P E ^a   Ferrandi, Fabrizio ^a   Pandini, Davide ^b   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

HASH-BASED APPROACH; LOGIC SYNTHESIS; TEMPLATE IDENTIFICATION;

ABSTRACTING; CONSTRAINT THEORY; FEATURE EXTRACTION;

LOGIC DESIGN;

EID: 36348975029     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.5     Document Type: Conference Paper

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