Regularity driven logic synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 439-446

  Kutzschebauch, Thomas ^a   Stok, Leon ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER AIDED DESIGN; DESIGN; LOGIC SYNTHESIS; SYNTHESIS (CHEMICAL); ALGORITHMS; AUTOMATION; DATA STRUCTURES; ERRORS;

DESIGN STAGE; GLOBAL DESIGN; LARGE DESIGNS; PHYSICAL DESIGN; REGULAR STRUCTURE; SPEED UP; SYNTHESIS PROCESS; TRIAL AND ERROR;

LOGIC DESIGN;

DATAFLOW AWARE SYNTHESIS; REGULARITY DRIVEN LOGIC SYNTHESIS;

EID: 0034483938     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896511     Document Type: Conference Paper

References (12)

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