Microstructure evolution and defect formation in Cu through-silicon vias (TSVs) during thermal annealing

Journal of Electronic Materials

Volumn 41, Issue 4, 2012, Pages 712-719

  Shin, Hae A Seul ^a   Kim, Byoung Joon ^a   Kim, Ju Heon ^b   Hwang, Sung Hwan ^a   Budiman, Arief Suriadi ^c   Son, Ho Young ^d   Byun, Kwang Yoo ^d   Tamura, Nobumichi ^e   Kunz, Martin ^e   Kim, Dong Ik ^b   Joo, Young Chang ^a  

^a Seoul National University   (South Korea)

^b Korea Institute of Science and Technology   (South Korea)

^c LOS ALAMOS NATIONAL LABORATORY   (United States)

^d Hynix Semiconductor Inc   (South Korea)

^e LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

copper; microstructure; stress; Through silicon via (TSV); twin

Indexed keywords

DEFECT FORMATION; GRAIN SIZE; LARGE-GRAIN; MICRO VOIDS; MICROSTRUCTURE EVOLUTIONS; STRESS LEVELS; STRUCTURAL STABILITIES; THERMAL-ANNEALING; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV); TWIN; TWIN BOUNDARIES;

COPPER; DEFECTS; ELECTRONICS PACKAGING; GRAIN GROWTH; GRAIN SIZE AND SHAPE; MICROSTRUCTURE; STABILITY; STRESS CONCENTRATION; STRESSES;

ANNEALING;

EID: 84862815488     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-012-1943-7     Document Type: Article

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