Design quality trade-off studies for 3-D ICs built with sub-micron TSVs and future devices

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 2, Issue 2, 2012, Pages 240-248

  Kim, Dae Hyun ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Device; interconnect; three dimensional integrated circuit (3 D IC); through silicon via (TSV)

Indexed keywords

3-D ICS; DELAY OVERHEADS; DESIGN QUALITY; DEVICE; DEVICE TECHNOLOGIES; IC LAYOUT; INTERCONNECT; PERFORMANCE IMPROVEMENTS; PROCESS TECHNOLOGIES; SIGNAL PATHS; SILICON AREA; SUBMICRON; THREE DIMENSIONAL INTEGRATED CIRCUITS; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV); TRADE-OFF STUDY; WIRE LENGTH;

CAPACITANCE; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; LIBRARIES;

THREE DIMENSIONAL;

EID: 84862325108     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2012.2193840     Document Type: Article

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