Impact of through-silicon-via scaling on the wirelength distribution of current and future 3D ICs

2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011

Volumn , Issue , 2011, Pages

  Kim, Dae Hyun ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3D TECHNOLOGY; PROCESS NODES; THROUGH-SILICON-VIA; WIRELENGTH DISTRIBUTION;

METALLIZING; TECHNOLOGY;

THREE DIMENSIONAL;

EID: 80052062511     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2011.5940324     Document Type: Conference Paper

References (3)

1. T. Thorolfsson, K. Gonsalves, and P. D. Franzon, "Design Automation for a 3DIC FFT Processor for Synthetic Aperture Radar: A Case Study," in Proc. ACM Design Automation Conf., July 2009, pp. 51-56.
2. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, "Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs," in Proc. ACM/IEEE Int. Workshop on System Level Interconnect Prediction, July 2009, pp. 85-92.
3. J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, "A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata," in Proc. IEEE Int. Interconnect Technology Conference, June 2000, pp. 126-128.