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Volumn , Issue , 2010, Pages

Timing analysis and optimization for 3D stacked multi-core microprocessors

Author keywords

[No Author keywords available]

Indexed keywords

CORE LEVELS; DESIGN METHODOLOGY; MULTI CORE; OVERALL DESIGN; PHYSICAL LAYOUT; TIMING ANALYSIS; TIMING CONSTRAINTS; TIMING OPTIMIZATION;

EID: 79955946162     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2010.5751444     Document Type: Conference Paper
Times cited : (18)

References (8)
  • 1
    • 61649096165 scopus 로고    scopus 로고
    • Wafer-level 3D integration technology
    • S. J. K. et al., "Wafer-level 3D integration technology," IBM Journal of Research and Development, vol. 52, no. 6, pp. 583-597, 2008.
    • (2008) IBM Journal of Research and Development , vol.52 , Issue.6 , pp. 583-597
    • K, S.J.1
  • 4
    • 46049113542 scopus 로고    scopus 로고
    • Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node
    • S.-M. J. et al., "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node," in International Electron Device Meeting, 2006, pp. 37-40.
    • International Electron Device Meeting, 2006 , pp. 37-40
    • J, S.-M.1
  • 5
    • 28144458334 scopus 로고    scopus 로고
    • Megapixel CMOS Image Sensor Fabricated in Three- Dimensional Integrated Circuit Technology
    • V. S. et al., "Megapixel CMOS Image Sensor Fabricated in Three- Dimensional Integrated Circuit Technology," in IEEE International Solid- States Circuits Conf., 2005.
    • IEEE International Solid- States Circuits Conf., 2005
    • S, V.1
  • 6
    • 80051985841 scopus 로고    scopus 로고
    • Online. Available
    • A. G. AB., "Leon3 Processor." [Online]. Available: http://www.gaisler.com/
    • Leon3 Processor
    • AB, A.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.