Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2011, Pages

  Kim, Dae Hyun ^a   Kim, Suyoun ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3D IC DESIGN; DESIGN QUALITY; DOWN-SCALING; IC LAYOUT; NANO SCALE; PROCESS TECHNOLOGIES; STANDARD CELL; SUBMICRON; THROUGH SILICON VIAS; WIRE LENGTH;

DESIGN; ELECTRIC BATTERIES; ELECTRIC POWER SYSTEM INTERCONNECTION; NANOTECHNOLOGY;

THREE DIMENSIONAL;

EID: 84863158556     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SLIP.2011.6135435     Document Type: Conference Paper

References (18)

1. T. Thorolfsson, K. Gonsalves, and P. D. Franzon, "Design Automation for a 3DIC FFT Processor for Synthetic Aperture Radar: A Case Study," in Proc. ACM Design Automation Conf., July 2009, pp. 51-56.
2. D. H. Kim, K. Athikulwongse, and S. K. Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout," in Proc. IEEE Int. Conf. on Computer-Aided Design, Nov. 2009, pp. 674-680.
3. D. H. Kim and S. K. Lim, "Through-Silicon-Via-aware Delay and Power Prediction Model for Buffered Interconnects in 3D ICs," in Proc. ACM/IEEE International Workshop on System Level Interconnect Prediction, June 2010, pp. 25-31.
4. M. Pathak, Y.-J. Lee, T. Moon, and S. K. Lim, "Through-Silicon-Via Management during 3D Physical Design: When to Add and How Many?" in Proc. IEEE Int. Conf. on Computer-Aided Design, Nov. 2010, pp. 387-394.
5. U. Kang et al., "8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology," in IEEE Journal of Solid State Circuits, no. 1, Jan. 2010, pp. 111-119.
6. G. V. der Plas et al., "Design Issues and Considerations for Low-Cost 3-D TSV IC Technology," in IEEE Journal of Solid State Circuits, no. 1, Jan. 2011, pp. 293-307.
7. S. Gupta, M. Hilbert, S. Hong, and R. Patti, "Techniques for Producing 3D ICs with High-Density Interconnect," in Proc. VLSI Multi-Level Interconnection Conf., 2004, pp. 56-59.
8. M. Koyanagi, T. Fukushima, and T. Tanaka, "High-Density Through Silicon Vias for 3-D LSIs," in Proceedings of the IEEE, no. 1, Jan. 2009, pp. 49-59.
9. nd Generation High-k + Metal Gate Transistors," in Proc. IEEE Int. Electron Devices Meeting, Dec. 2009.
10. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, "Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs," in Proc. ACM/IEEE International Workshop on System Level Interconnect Prediction, July 2009, pp. 85-92.
11. Tezzaron, "Tezzaron/MOSIS MPW Run," http://www.tezzaron.com.
12. PTM, "Predictive Technology Model," http://ptm.asu.edu.
13. P. Bai et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0:57μm2 SRAM Cell," in Proc. IEEE Int. Electron Devices Meeting, Dec. 2004.
14. K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," in Proc. IEEE Int. Electron Devices Meeting, Dec. 2007.
15. Nangate, "The Nangate 45nm Open Cell Library," http://www.nangate.com.
16. Cadence, "Soc Encounter," http://www.cadence.com.
17. Y.-J. Lee and S. K. Lim, "Timing Analysis and Optimization for 3D Stacked Multi-Core Microprocessors," in IEEE Int. 3D System Integration Conf., Nov. 2010.
18. Synopsys, "Primetime," http://www.synopsys.com.