Validation of hardware error recovery mechanisms for the SPARC64 v microprocessor

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2008, Pages 62-69

  Ando, Hisashige ^a   Kan, Ryuji ^a   Tosaka, Yoshiharu ^a   Takahisa, Keiji ^b   Hatanaka, Kichiji ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEM RECOVERY; ERROR CORRECTION; FAILURE ANALYSIS; LOGIC CIRCUITS; NEUTRONS; RADIATION HARDENING; RECOVERY; UNIX;

ATMOSPHERIC NEUTRONS; CIRCUIT FAULTS; ERROR DETECTION AND RECOVERY; ERROR RECOVERY MECHANISMS; FAILURE RATE; HARDWARE ERROR; HARDWARE MECHANISM; HIGH RELIABILITY;

COMPUTER CIRCUITS;

EID: 53349142161     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2008.4630071     Document Type: Conference Paper

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