A scalable memory-based reconfigurable computing framework for nanoscale crossbar

IEEE Transactions on Nanotechnology

Volumn 11, Issue 3, 2012, Pages 451-462

  Paul, Somnath ^a   Bhunia, Swarup ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Field programmable gate array (FPGA); memory based computing; nanoscale crossbar; reconfigurable architecture

Indexed keywords

COMPUTING ELEMENT; CROSS-BAR STRUCTURES; DEFECT TOLERANCE; DESIGN CHALLENGES; ELECTRONIC SYSTEMS; LOGIC BLOCKS; LOGIC FUNCTIONS; MEMORY ARRAY; MEMORY DESIGN; MEMORY-BASED COMPUTING; MOLECULAR CROSSBARS; MOLECULAR ELECTRONIC DEVICE; MULTI-INPUT MULTI-OUTPUT; NANO SCALE; NANO-COMPUTING; NANOSCALE CROSSBAR; PROGRAMMABLE INTERCONNECTS; RECONFIGURABLE COMPUTING; TIME MULTIPLEXED;

DISCRETE COSINE TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NANOTECHNOLOGY; RECONFIGURABLE ARCHITECTURES;

MEMORY ARCHITECTURE;

EID: 84860863038     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2010.2041556     Document Type: Article

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